應用於5G通訊Ka頻段之功率偵測電路

Ka-band Power Detectors for 5G Communication

陳瑀妮(Yu-Ni Chen)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201703907

摘要

本論文主要研究5G頻段功率偵測系統相關電路，操作頻率為Ka頻段，用於提升偵測能力並確認發射端系統的特性。本論文首先回顧各功率偵測相關電路文獻，接著介紹其運作原理，包含偵測器、低雜訊放大器及混頻器，簡介不同設計目的之功能及架構。接著介紹不同類型的低雜訊放大器設計方法，包含共源放大器、連續及分段式可變增益低雜訊放大器，最後是次諧波降頻混頻器。
本論文首先提出一固定增益值之共源低雜訊放大器，利用源極電感及疊接放大器方法達到高增益及低雜訊目標，量測結果可達到13.5 dB的增益，最後更結合自混式整流器及運算放大器形成一完整偵測器，可偵測之最小功率可達-38 dBm，輸出直流電壓範圍為125 mV至720 mV，直流功耗為31.5 mW。為了提升偵測區間，本研究設計一連續可變增益之低雜訊放大器，透過增益的改變可以增加偵測器的偵測動態區間，放大率由小到大能偵測由大至小的輸入功率，此放大器特點為功耗極低，約為9 mW。第二版電路為了能精確地由輸出偵測電壓推回輸入訊號功率大小，提出一個三段式可調的低雜訊放大器，使用電流回授技術降低雜訊及提升增益，亦結合迪克誤差消除電路，透過開關的切換平均並消除此隨機雜訊，達到19 dB的增益同時雜訊指數6.3 dB(含開關)。此外，為了降低射頻訊號偵測難度及增加動態區間，本論文亦提出一次諧波降頻混頻器，透過射頻端的變壓器技術達到與本地端隔離度接近60 dB、輸入1 dB截止點為-3 dBm。
本論文採用Advanced Design System(ADS)軟體進行電路模擬，被動走線及其他元件之電磁響應模擬則使用Sonnet軟體。而本文所提之四個主要電路分別是台積電之180 nm之低雜訊放大器，晶片面積為525 μm x 645 μm、90 nm CMOS製程之第一版連續可變增益放大器面積為320 μm x 680 μm、第二版數位可變增益放大器395 μm x 515 μm以及次諧波降頻混頻器660 μm x 580 μm。晶片量測與模擬結果大致吻合，結果討論及模擬修正將於第四章節中探討。

關鍵字

低雜訊放大器 ； 迪克開關 ； 次諧波混頻器 ； 功率偵測電路 ； 可調增益低雜訊放大器 ； 5G通訊

並列摘要

This thesis studies power detectors, which operate in Ka-band for 5G communication and are proposed to enhance detection capability and verify the property of transmitter systems.
First, this thesis reviews the architectures of different types of circuits related to power detectors, including detectors, low noise amplifiers and mixers. In addition, this study analyzes the operation principles as well as briefly introduces the functions and applications of the circuit design. Second, the thesis introduces different types of design methods of the common-source amplifier, the continuous variable gain amplifier, the digitally-controlled variable gain amplifier and the subharmonic down-convert mixer.
This thesis first proposes a fixed gain common-source amplifier. With source degeneration techniques and cascade structure, it achieves high gain of 13.5 dB and low noise. Moreover, it is also integrated with a self-mixing rectifier and an operational amplifier to form a detector with minimum detectable power of -38 dBm. Its DC voltage output range is from 125 mV to 720 mV and power consumption is 31.5 mW. In order to increase its detectable range, we also redesigned a continuous variable gain amplifier. With the increase of gain, smaller power is detectable, and the amplifier consumes only 9 mW power. The second version of VGLNA introduces a digitally-controlled three state variable gain amplifier and applies current-reused technique to reduce noise as well as to enhance gain. Besides, a Dicke switch is also integrated to average and cancel out the flicker noise of transistors, and the design achieves 19 dB gain with noise figure at only 6.3 dB (with switch). On the other hand, to simplify detection and increase dynamic range, this study also proposes a subharmonic down-convert mixer, which realizes 2LO to RF isolation of nearly 60 dB and IP1dB at -3 dBm with transformer.
In this thesis, the proposed circuits were designed by using ADS and Sonnet for the circuit and EM simulation. The four circuits were: an LNA implemented by TSMC 180 nm CMOS, a continuous VGLNA, a digitally-controlled VGLNA and a subharmonic mixer in CMOS technology 90 nm. The measurement results almost fit the simulation and discussions are given in Chapter 4.

並列關鍵字

low noise amplifier ； Dicke switch ； subharmonic mixer ； 5G communication ； power detector ； variable-gain low noise amplifier

參考文獻

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