應用於28 GHz 5G通訊的功率分配器、可變增益低雜訊放大器及降頻混波器之研究

Power Dividers, Variable-Gain Low-Noise Amplifiers, and Down-Conversion Mixer for 28 GHz 5G Communications

陳柏舜(Bo-Shun Chen)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2022年)

https://doi.org/10.6837/ncnu202200003

摘要

本論文探討應用於5G通訊應用設計，第一個部分是，我們介紹了同相單螺旋Ka波段(26.5-40 GHz) CMOS 威爾金森功率分配器及其衍生正交耦合器(QC)和巴倫的設計和分析。對於功率分配器，在輸入端口並聯一個電容器用於輸入匹配，並在輸出端口之間連接一個並聯RC網絡用於輸入匹配和隔離。採用傳輸線(TL)長度約為λ/12的同相單螺旋結構，實現微型面積和小幅度不平衡(AI)和相位差(PD)。為了實現QC和巴倫，可以在功率分配器的2和3端口包含分別具有-45°/45°和-90°/90°相移的負/正相移TL。第二部分，介紹了一種對稱佈局的基於反向耦合線的毫米波CMOS威爾金森功分器。螺旋耦合線，即具有互感的兩條反向螺旋傳輸線(TL)，可將RC隔離網絡所需的C降低至較小或可忽略的值(即，C是不可能的)。功率分配器可顯著减少TL長度(從λ/4至λ/9)由於集中分佈結構和對稱佈局，振幅不平衡(AI)和相位差(PD)增强。第三部份，我們設計了雙圈對稱螺旋耦合線SPDT、最小同相單螺旋耦合線SPDT、最小反向耦合線SPDT和反相耦合線SPDT，四種SPDT開關設計。對於功率分配器，在輸入端並聯電容，以補償輸入導納的虛部以進行輸入匹配。對於SPDT開關，在1到3端處並聯電容，以減少等校電路所需的TL長度λ/4用於緊湊尺寸。第四部份，我們使用了0.18 um 製程設計了3級可變增益低雜訊放大器，也使用了90 nm 製程設計可變增益低雜訊放大器，具有低雜訊3.489 dB、增益20.072 dB和低功耗5.808 mW。90 製成的28 GHz 混頻器，具有13.426 dB高增益，11.5 dB 低雜訊和混頻器前端使用小面積威爾金森功率分配器相位差巴倫設計。

關鍵字

毫米波 ； 微型 ； 威爾金森功率分配器 ； 緊湊 ； 螺旋 ； 對稱 ； 耦合線 ； 毫米波 ； 可變增益低雜訊放大器 ； 雜訊 ； 低功率 ； 共源共柵 ； 共源放大器 ； 混頻器

並列摘要

In the first part, we present the design and analysis of noninverting single-spiral Ka-band (26.5-40 GHz) CMOS Wilkinson power dividers and their deriving quadrature couplers (QCs) and baluns. For the power dividers, a parallel capacitor is included at the input port (port 1) for input matching, and a parallel RC network is connected between the output ports (ports 2 and 3) for input matching and isolation. Noninverting single-spiral structure with transmission-line (TL) length of about λ/12 is adopted to achieve miniature area and small amplitude imbalance (AI) and phase difference (PD). To realize QC and balun, negative/positive phase-shift TLs with phase-shift of -45°/45° and -90°/90°, respectively, can be included at ports 2 and 3 of the power divider. Two power dividers and their deriving two QCs and two baluns are designed and implemented. In second part, An inverting-coupled-line-based millimeter-wave CMOS Wilkinson power divider with symmetrical layout is demonstrated. The spiral coupled line, i.e. two inverting spiral transmission lines (TLs) with a negative mutual inductance, can reduce the required C of the RC isolation network to a small or negligible value (i.e. C is omissible). The power divider achieves significant TL-length reduction (from λ/4 to λ/9) and amplitude imbalance (AI) and phase difference (PD) enhancement due to the lumped-distributed structure and symmetrical layout.

In third part, we used Dual SPDT, Min noninverting SPDT, Min inverting SPDT and Inverting SPDT four SPDT designs. For the power divider, a parallel capacitor is included.
In four part, we used 3 Stage VGLNA designed with 0.18 um process. Designed with 90 nm process VGLNA. The simulated noise figure 3.489 dB, the gain 20.072 dB, the power consumption is 5.808 mW. Mixer in 90 nm CMOS for 28 GHz, high gain of 13.426 dB, Low noise of 11.5 dB and small area Wilkinson power divider phase difference balun on the front end of Mixer.

並列關鍵字

Millimeter-wave ； miniature ； Wilkinson power divider ； compact ； spiral ； symmetrical ； coupled line ； millimeter-wave ； variable gain low noise amplifier ； noise figure ； low power ； cascode ； common source amplifier ； mixer

參考文獻

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