垂直堆疊式互補式錫氧化物薄膜電晶體反相器電路之研究

Vertically-Stacked Complementary Inverters Composed of Tin-Oxide-Based Thin-Film Transistors

楊皓麟(Hao-Lin Yang)

指導教授 ： 陳奕君

國立臺灣大學/電機資訊學院/光電工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201703985

摘要

本研究以低溫製程，開發出垂直堆疊式互補式錫氧化物反相器電路元件，並同時為首次以相同氧化物材料基底實現垂直結構互補式反相器之研究。實驗過程分別針對上閘極p型、下閘極n型之錫氧化物薄膜電晶體之元件特性進行優化，垂直堆疊式互補式反相器是由n型薄膜電晶體堆疊在p型薄膜電晶體之上所組成，故實驗過程討論亦包含n型薄膜電晶體製程對於上閘極p型薄膜電晶體特性之影響。
　　實驗中採用金屬錫作為靶材，利用射頻磁控濺鍍系統於室溫下沉積錫氧化物薄膜，並以相同濺鍍條件成長p型與n型薄膜電晶體之通道層。在上閘極p型薄膜電晶體部分，沉積15 nm錫氧化物薄膜後分別在175℃、185℃、195℃、205℃、215℃、225℃溫度下進行持溫30分鐘退火，結果發現在覆蓋原子層沉積二氧化鉿介電層後，主動層退火溫度為195℃之情形下，具最顯著之氧化亞錫(101)結晶相繞射峰，所製作之上閘極p型電晶體亦擁有最佳電性表現。在n型下閘極薄膜電晶體方面，則利用二氧化鋯覆蓋層搭配後退火製程的氧化效應將p型錫氧化物薄膜轉為n型，為提升電晶體載子遷移率而進行通道層厚度的調變，分別嘗試15 nm、17.5 nm、20 nm、22.5 nm四種厚度，結果顯示厚度愈厚，載子遷移率愈大，但厚度為20 nm時關電流會大幅上升，為了兼顧良好載子遷移率與電流開關比，因此選擇17.5 nm作為n型電晶體之通道層厚度。值得一提的是，下方之上閘極p型電晶體電性並不受上部之n型錫氧化物薄膜電晶體製作程序所影響，顯示出原子層沉積系統成長之二氧化鉿介電層對錫氧化物薄膜具有良好封裝特性。
　　接著利用垂直通孔與互連導線的方式，串接p型與n型氧化物薄膜電晶體形成垂直堆疊式CMOS反相器。在製作全錫氧化物互補式反相器前，先以本研究團隊先前開發之氧化鋅(ZnO)作為n型電晶體之通道層，藉此測試光罩設計及堆疊結構之製程。由p型SnO及n型ZnO所組成之垂直堆疊式CMOS反相器，其電性結果如附錄II所示。當反相器中p型與n型元件通道幾何長寬比(W/L)p/(W/L)n為5且電源供應VDD為10 V時，其電壓增益達56.1 V/V，此結果已高於已知文獻中全氧化物半導體互補式反向器之最高電壓增益30 V/V。最後將p型與n型錫氧化物薄膜電晶體整合，製作垂直堆疊式全錫氧化物互補式反相器，當反相器中p型與n型元件通道幾何長寬比(W/L)p/(W/L)n為5且VDD為10 V時，CMOS反相器電壓增益達15.5 V/V，此時高準位雜訊邊界(NMH)與低準位雜訊邊界(NML)分別為4.9 V與3.2 V；而在VDD為8 V時，其電壓增益會稍降至13.6 V/V，其高準位雜訊邊界(NMH)與低準位雜訊邊界(NML)分別為3.2 V與3.1 V，此時雜訊邊界接近於理想值 VDD/2，故反相器在此操作點下，具較佳的雜訊容忍度，適合進一步應用於薄膜電路上。

關鍵字

錫氧化物 ； 薄膜電晶體 ； 氧化物半導體 ； 垂直堆疊式互補式反相器

並列摘要

In this research, a vertically-stacked complementary inverter composed of a bottom-gate n-type tin oxide (SnOx) thin-film transistor (TFT) and a top-gate p-type SnOx TFT processed at low substrate temperatures was demonstrated. It is the first vertically-stacked complementary oxide-TFT based inverter using the same material system reported. The process parameters of the top-gate p-type SnOx TFT and the bottom-gate n-type SnOx TFT were optimized individually. Then the influence of the subsequent process for fabricating the n-type bottom-gate SnOx TFT on the electrical performance of the underlying top-gate p-type TFT was investigated.
　Both the SnOx active layers for the p-type and n-type TFTs were deposited by room-temperature rf-magnetron sputtering using the same deposition condition. To optimize the top-gate p-type TFT, the 15-nm-thick as-deposited SnOx thin films were thermally annealed at various temperatures (175, 185, 195, 205, 215 and 225°C) for 30 min. After the subsequent deposition of a 50-nm-thick hafnium oxide (HfO2) gate dielectric by atomic layer deposition (ALD), the 195°C-annealed SnOx thin film has the strongest diffraction peak of SnO (101) among all. The corresponding top-gate p-type SnOx TFT also exhibits highest field-effect mobility.
　The bottom-gate n-type SnOx TFT was realized by the zirconium dioxide (ZrO2) capping layer assisted oxidation effect of the SnOx channel. The effect of active layer thickness (15, 17.5, 20 and 22.5 nm) on the TFT performance was investigated. When the thickness increases, both the field-effect mobility and off current of the TFT increase. To compromise between the field-effect mobility and on/off current ratio, an active layer with thickness of 17.5-nm was eventually adopted. It is worth to point out that the subsequent processing steps for fabricating the n-type SnOx TFT had no obvious impact on the performance of the previously-fabricated underlying top-gate p-type TFT, implying the ALD-HfO2 layer serves as a good encapsulant in addition to a gate dielectric.
　The p-type and n-type TFTs were then interconnected through a via-hole to form the vertically-stacked complementary inverter. Prior to the fabrication of fully tin oxide-based complementary inverters, the n-type zinc oxide (ZnO) TFT developed previously in our group was used in conjunction with the p-type SnOx TFT to test the mask design and process flow for the stacked CMOS inverter. The electrical characteristics of the vertically-stacked CMOS inverters consisting of p-type SnOx and n-type ZnO TFTs were summarized in Appendix II. At VDD of 10 V, the CMOS inverter with a geometric aspect ratio of 5 exhibits a voltage gain of 56.1 V/V, which is higher than that of the fully oxide-based CMOS inverter reported before. We then integrated the top-gate p-type SnOx TFT with the bottom-gate n-type SnOx TFT to form the vertically-stacked fully tin oxide-based complementary inverter. The voltage gain of an inverter with a geometric aspect ratio of 5 reaches ~15.5 V/V at VDD = 10 V, and the noise margin high (NMH) and noise margin low (NML) are 4.9 V and 3.2V, respectively. At VDD of 8 V, more balanced noise margins with NMH and NML of 3.2 V and 3.1 V are achieved despite a slightly smaller voltage gain of 13.6 V/V. At this operating point, the SnOx-TFT-based vertically-stacked complementary inverter exhibited better noise immunity as a more feasible logic element for thin-film circuitry.

並列關鍵字

tin oxide (SnOx) ； thin-film transistor (TFT) ； oxide-semiconductor ； vertically-stacked complementary inverter

參考文獻

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[3] J. E. Lilienfeld, "Amplifier for electric currents," U.S. Patent 1877140, 1932.

[4] J. E. Lilienfeld, "Device for controlling electric current," Patent 1900018, 1933.

[5] P. K. Weimer, "The TFT a new thin-film transistor," Proceedings of the IRE, vol. 50, no. 6, pp. 1462-1469, 1962.