This thesis proposes a die-to-die communication mechanism. Its transmitting medium is a common-resistive layer. In the transmitter design, to boost the operating speed and reduce leakage power originated from the neighboring pads, a dual-NMOS driver is used. In the receiver design, to compensate for the insufficient voltage level in the channel-output node when the circuit is operated at high speed, a double-feedback compensating mechanism is adopted. This interconnect has energy efficiency of 0.16 pJ/bit at 1.25 Gbps. The proposed vertical signal transmission method is simulated in TSMC 0.18-um process for demonstration of the architecture.