使用於IEEE 802.11n規範中之低密度同位檢查碼解碼器硬體架構設計

A Hardware Architecture Design of the Low-Density Parity-Check Code Decoder for IEEE 802.11n Standard

童柏文(Bo-Wen Tung)

指導教授 ： 林茂昭

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.02279

摘要

現今的LDPC 解碼器在實作上所面對的其中一個主要的挑戰乃在於，隨著平行處理單元的增加，其內部的連線複雜度亦隨之上升，進而使得晶片整體的面積、延遲以及功耗跟著增加。在此篇論文中，為了能獲得由Mosehnin 提出的split-row threshold algorithm 對硬體所帶來的好處，以及保留住802.11n 標準中所定義的LDPC碼的優異糾錯能力，我們提出了一個採用縮減量化法的分核架構。而實作的結果顯示，在繞線階段前的面積相近的情況下，採用我們所提出之架構的解碼器的面積為2.58平方公厘，並且可達到85%的利用率，而採用傳統未分割的架構的解碼器其利用率僅達70%，面積則為3平方公厘。

關鍵字

低密度同位檢查碼 ； 802.11n ； 最小和演算法 ； 排列式加速解碼 ； 分割列-臨界演算法 ； 降低繞線壅塞

並列摘要

One of the main challenges of implementing an LDPC code decoder is that the interconnection
complexity is growing along with the number of the parallel processing
units, which results in the increased delay, power dissipation, and chip area. In this
thesis, we propose a design called split-core architecture with reduced-quantization method which reserves the benefit of split-row threshold algorithm proposed by Mohsenin and simultaneously retains the good error performance for a multi-mode LDPC decoder of 802.11n standard. The implementation results show that the area of a decoder with our proposed architecture is 2.58 mm2 with a final core utilization of 85%, as compared to the area of 3 mm2 and a core utilization of 70% for the non-splitting architecture, while the area sizes are similar for both architectures before the routing process.

並列關鍵字

low-density parity check code ； 802.11n ； min-sum algorithm ； permuted accelerated decoding ； split-row threshold algorithm ； routing congestion reduction

參考文獻

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