可程式化通訊處理器之架構設計與分析

隨著科技的進步，行動裝置的功能越來越強，也讓一個手持裝置可能同時支援許多無線通訊系統。現今的做法都是整合許多專用集成電路，一個負責一種通訊協定，來提供所需的多種傳輸模式功能。然而，當越來越多的通訊協定必須加入到一個手持裝置時，這就不再是一個非常有效率而且足夠彈性的做法。軟體無線電技術就是希望利用一個可程式化的處理器來即時的重新編組以切換所支援的無線通訊系統。隨著未來的通訊系統複雜度越來越高，可編程的處理器必須提供每秒一千億個運算能力才能符合需求，而現今主流的超長指令字訊號處理器卻無法提供這樣的運算能力。因此，我們需要研究一種新的架構能同時符合龐大的運算能力要求但又能提供足夠的編程彈性。可重置架構因為可以有效的利用許多運算元因而被嚐試應用到軟體無線電中。而其運算元從簡單的一個算術邏輯元件到完整的一個處理器都涵括在可重置架構的範疇中。我們在這篇論文中就分析了一些常見的通訊演算法，並提出一個基於可重置架構的通訊處理器。我們將所有的算術邏輯元件以一個共同的數據傳輸線連結起來，形成一個在邏輯上排列成一維陣列的架構。此架構非常適合用於運算有限脈衝響應濾波器之實現以及一些矩陣運算。另外，此架構也包含一個可編程的資料交換傳輸線，能有效的將運算元中的暫存資料做交換。

關鍵字

軟體無線電；處理器架構；可重置架構；通訊處理器

並列摘要

Nowadays, mobile devices are incorporated with more and more communication standards. Currently, several ASICs are combined to support the multi-mode operation in a mobile device. However, this is neither an efficient nor a flexible solution when more radio interfaces are added. Software-Defined Radio tends to use programmable processors to reconfigure on the fly and switch from one radio interface to another. With future communication standards having computation complexity up to 100s and even 1000s of GOPS, current DSP processors with VLIW architecture will not be able to meet the real-time requirements. This requires the research for a more suitable architecture for communication related algorithms. Coarse-grained reconfigurable architectures have gain attention in the application of SDR. This class of processors embeds a large amount of processing units arranged in a 1D/2D array. The granularity of processing elements spreads over a wide range, from an ALU to a simple RISC processor. They tend to provide t of processing power by incorporating many functional units. Inspired by reconfigurable architectures, we propose architecture consists of a wide 1D ALU array, which tends to compute each operation related to the input data simultaneous. This kind of computation is suitable for FIR filtering, matrix-vector multiplications and other digital communication algorithms. A global data bus is used to broadcast inputs to all PEs and a reconfigurable data exchange bus is utilized to pass data between ALUs, which tends to compute each operation related to the input data simultaneous. This kind of computation is suitable for FIR filtering, matrix-vector multiplications and other digital communication algorithms. A global data bus is used to broadcast inputs to all PEs and a reconfigurable data exchange bus is utilized to pass data between ALUs.

並列關鍵字

Software defined radio ； Processor architecture ； Reconfigurable architecture ； Communication processor

參考文獻

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[3] J. Mitola III. “Cognitive Radio Architecture,” Wiley, 2006.

[6] M. H. Wu, “A Reconfigurable Architecture for OFDM-based Wireless Communication Systems,” MS Thesis, National Taiwan University, Taipei, 2005.

[7] R. Baines, and D. Pulley, "A Total Cost Approach to Evaluating Different Reconfigurable Architectures for Baseband Processing in Wireless Receivers," Communications Magazine, IEEE , vol.41, no.1, pp. 105-113, Jan 2003.

[8] Z. Salcic, and C.F. Mecklenbrauker, "Software Radio - Architectural Requirements, Research and Development Challenges," The 8th International Conference on Communication Systems, vol.2, no., pp. 711-716 vol.2, 25-28 Nov. 2002.

國際替代計量

可程式化通訊處理器之架構設計與分析

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