使用貝氏訊號機率模型的轉態延遲錯誤測試圖樣產生技術

Transition Delay Fault Test Pattern Generation Using a Bayesian-Based Signal Probability Model

鄭景鴻(Ching-Hung Cheng)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202003938

摘要

現代的高效能積體電路對於操作頻率的需求逐年提升，也因此對於延遲錯誤的偵測需求愈發重視。基於全掃描鍊的轉態延遲錯誤測試是一種廣泛被使用於偵測延遲錯誤的方法。在傳統的測試品質項目中，錯誤涵蓋率與測試圖樣數目是最重要的指標。最近的趨勢則是更進一步要求測試過程中的電力消耗與正常操作模式時相近—過高與過低的電力消耗分別會造成過度測試與測試逃脫的問題。
本論文所提出的轉態延遲錯誤自動化測試圖樣產生器以基於貝氏理論的訊號機率模型取代傳統的COP與SCOAP可測試性指標，藉以提高測試圖樣的錯誤偵測能力並使其功率消耗更接近正常的模式。貝式訊號機率模型因為考慮電路裡常見的重收斂扇出，因此比COP與SCOAP更精確的預測電路行為。在產生測試圖樣的過程中，這可以降低錯誤的決定，因此提高錯誤偵測率。此外，我們亦使用基於貝氏理論的訊號機率模型來設定ATPG未指定的信號值。實驗結果顯示，採用貝氏理論訊號機率模型確實能提高錯誤偵測率並降低測試功率。

關鍵字

自動圖樣測試產生系統

並列摘要

With the growing operating frequencies of modern high-performance ICs, delay fault testing becomes mandatory. Currently, transition delay fault is the most popular delay fault mode. In the past, fault coverage and test size are the two most important test quality metrics. Recently, it is further required that test power consumption be similar to the functional mode power consumption — excessive test power consumption has been known to cause overkill; low test power consumption, on the other hand, may cause test escape.
In this thesis, we propose to replace the conventional COP and SCOAP testability measure with Bayesian-based signal probability model. The goal is to improve the test pattern set quality and to produce a more functional-like power consumption behavior. Being re-convergence aware, the Bayesian-based signal probability model can more accurately predict circuit behavior. As a result, it reduces the possibility of conflicting PI/PPI assignments and improves fault detection efficiency. Furthermore, we also utilized the Bayesian model to guide the X-fill process. Experimental results show that the proposed ATPG improves fault coverage and lowers test power consumption.

並列關鍵字

Automatic Test Pattern Generation

參考文獻

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