透過您的圖書館登入
IP:3.149.251.155
  • 學位論文

基於轉移函式理論之錯誤模型 類比電路最佳測試信號設計

Efficient test stimulus design for continuous-time LTI analog circuits using the transfer function based analog fault model

指導教授 : 洪浩喬
本文將於2024/10/29開放下載。若您希望在開放下載時收到通知,可將文章加入收藏

摘要


隨著對產品功能需求的提升,現今一顆小小的IC裡的功能越來越多,也越來越複雜,任何一顆電晶體或是系統I/O間發生問題,都可能會使的整個系統功能發生錯誤。為了確保產品的可靠度與品質,目前業界所採用的測試方法,需要掃描所有測試點(頻率),判斷所有的測試點的響應是否落在設計視窗裡,其中所需花費的測試時間和測試成本幾乎占整個晶片成本的大半部分,這對於時間就是金錢的藍海競爭市場而言是相當致命的。除此之外,由於缺乏有效的類比錯誤模型,功能性測試無法保證測試點與測試點之間的頻率響應是否符合測試結果。因此亟需一個簡單又準確的類比錯誤模型在簡化測試且降低測試成本的同時,又能確保測試的品質就需要一個簡單又準確的錯誤模型。本論文根據基於轉移函式的類比錯誤模型提出最適合類比電路的測試信號設計,此測試信號能夠抗拒測試雜訊,所提出之測試方法能夠使用最少的測試時間並且可以完整呈現頻率響應。

並列摘要


How to efficiently test analog circuits is an open issue because of the lack of widely-accepted analog fault model. This research project studies the impacts of the parametric faults on the transfer function’s coefficients of continuous-time and linear-and-time invariant (LTI) analog circuits from the design’s point of view. It is found the parametric faults change the coefficients but not the template of the transfer function (TF) of the circuit under test (CUT). Based on this observation, a test procedure that does not need time-consuming fault simulations is proposed. We show the practical TF coefficients of the CUT can be accurately measured by conducting a simple multi-tone test. In addition, conventional coefficient based tests make pass/fail decisions by checking if any coefficient is outside its pre-computed tolerance box. From the design’s point of view, we propose comparing the frequency responses of the measured TF with the design specification to make the final pass/fail decision, the same as what conventional functional tests do.

並列關鍵字

fault modal test stimuli design

參考文獻


[1] J. W. Bandler and A. E. Salama, "Fault diagnosis of analog circuits," Proceedings of the IEEE, vol. 73, no.8, Aug. 1985, pp. 1279-1325.
[2] N. Nagi, A. Chatterjee, A. Balivada, and J. A. Abraham, "Fault-based automatic test generator for linear analog devices," in Proc. International Conference on Computer-Aided Design (ICCAD), 1993, pp. 88-91.
[3] H.−C. Hong, “A static linear behavior analog fault model for switched− capacitor circuits,” IEEE Transactions on Computer-Aided Design (TCAD), vol. 31, no. 4, pp. 597–609, 2012.
[4] L.-T. Wang, C.-W. Wu and X.-G. Wen, Design for Testability: VLSI Test Principles and Architectures. San Francisco, CA:Morgan Kaufmann publishers Inc., Sep. 2006.
[5] J. Knaizuk and C. Hartman, “A optimal algorithm for testing stuck-at faults in random access memories,” IEEE Transactions on Computers (TC), vol. 26, no. 11, pp. 1141–1144, Nov 1977.

延伸閱讀