百億位元乙太被動光纖網路分碼多工接收機前端電路之設計與實作

Design and Implementation of Front End Circuit for Optical CDMA-Based Gigabit-EPON Receiver

謝明志(Ming-Chih Hsieh)

指導教授 ： 曹恆偉

國立臺灣大學/電機資訊學院/光電工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.01163

摘要

光纖通訊是能夠提供低成本及大容量通訊的最佳方案，近幾年為了滿足對頻寬不斷增加的需求，資料傳輸已步入了每秒百億位元的速度，骨幹網路和區域網路都有很大進展，達到了每秒百億位元的速度，然而，在兩者之間卻存有一個鴻溝，因為介於兩者之間的擷取網路，其速度並沒有隨著提升，就研究顯示，被動式光網路是寬頻擷取網路的最好選擇，可以連接這兩者之間的鴻溝。
光分碼多工乙太被動光網路是乙太被動光網路的一個改良版本，能對頻寬作更有效的利用，本篇論文將討論光分碼多工乙太被動光網路接收機前端電路的設計及實作，兩個不同速度的版本將在本論文中討論，第一部份是操作在 1.25Gb/s的速度之下，利用 0.35-μm CMOS製程，將前端類比電路和類比相關器整合在單一晶片上，前端電路包含轉阻放大器、可變增益放大器和後端放大器，這前端電路具備有高度的動態範圍來保持收入訊號的線性度完整性，模擬結果顯示，整個前段電路的增益有 78.8dB，頻寬約為 1.27GHz，在輸入 3.3 伏特的電壓下，總消耗功率為452 毫瓦，全部的晶片面積佔了 1.0 × 1.4 mm2。
另一個操作在10Gb/s 的版本，前端類比電路和類比相關器同樣地整合在單一晶片上，使用0.18-μm CMOS 製程來實現，該前端電路由轉阻放大器及兩個後級放大器組成，在此我們提出一個新的電路架構，讓轉阻放大器能在不使用電感的情況之下，操作在10Gb/s 的速度，而在後級放大器的設計上，我們提出一個未使用電感的電路技巧，而能提昇寬頻放大器約 25% 的頻寬，整個前端放大器利用這兩個特殊的電路架構，能使速度達到 10Gb/s 而無須使用電感，從模擬結果得知，整個前端電路的轉阻增益約有 72dB ，頻寬約為 8.2GHz，在輸入電壓為 1.8 伏特的情形下，共消耗 184 毫瓦的功率。

關鍵字

光纖通訊 ； 光接收機 ； 前端電路 ； 被動光網路 ； 乙太被動光網路 ； 光分碼多工 ； 轉阻放大器 ； 類比相關器

並列摘要

Fiber-optic communication system is the best solution for large-capacity and low-cost communication. Recently, the data transmission has entered the gigabit domain to meet the increasing demand of the bandwidth. The backbone network and the Local-Area Network (LAN) have a great advance up to tens of gigabit per second. However, there is still a gap between backbone and LAN. The progress in access network doesn’t keep with the great advance of backbone and LAN. This is a well-known problem, “the First Mile”. A passive optical network (PON) is investigated as the best candidate for the access network, which can bridge this gap.
An Optical CDMA-based EPON is a modified version of EPON, which can utilize the bandwidth better than EPON. In this work, the front end circuit of OLT receiver for Optical CDMA-based EPON system is designed and implemented. Two versions of different speed are included in this thesis. The middle-speed version operates at the rate of 1.25Gb/s. This receiver integrates the analog front end and the analog correlateor on the same chip and fabricated in the 0.35-μm CMOS process. The front end including transimpedance amplifier (TIA), variable gain amplifier (VGA) and post amplifier has a wide dynamic range to preserve the linearity of the received signal. The simulated
results report the front end has the transimpedance gain of 78.7dB over the bandwidth of 1.27GHz. Under the supply voltage of 3.3V, the whole chip dissipates the power of
452mW. And the whole chip occupies the area of 1.0 × 1.4 mm2.
For the high speed version, the front end circuit operates at the speed of 10Gb/s.The analog front and the analog correlator are also integrated on a single-chip but
implemented in 0.18-μm CMOS technology. The analog front end is composed of TIA and two post amplifiers. For TIA, a novel topology is proposed and makes the TIA able to operate at the rate of 10Gb/s without the aid of inductor. And an inductorless circuit technique is explored and improves the bandwidth of the broadband amplifier gain cell
about 25%. With the aid of novel circuit technique, the analog front end can operate at the rate of 10Gb/s without the usage of inductor, saving the whole chip area dramatically. The simulated results tell us that the analog front end has the transimpedance gain of 63dB over the bandwidth of 8.1GHz. With the 1.8V supply voltage, the whole receiver exhibits the power dissipation of 184 mW.
Index Terms – Optical communication, optical receivers, optical front-end circuit, passive optical network (PON), Ethernet passive optical network (EPON), Optical CDMA, transimpedance amplifier (TIA), analog correlator.

並列關鍵字

Optical communication ； optical receivers ； optical front-end circuit ； passive optical network (PON) ； Ethernet passive optical network (EPON) ； Optical CDMA ； transimpedance amplifier (TIA) ； analog correlator

參考文獻

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