寬頻頻率轉換電路之研製

Design and Implementation of Broadband Frequency Conversion Circuits

顏暐翰(Wei-Han Yen)

指導教授 ： 王紳

國立臺北科技大學/電資學院/電腦與通訊研究所 電子電腦與通訊產業研發碩士專班/碩士(2014年)

https://doi.org/10.6841/NTUT.2014.00905

摘要

本篇論文採用台積電提供之CMOS 0.18 微米製程設計寬頻頻率轉換電路，其中所呈現的電路包含：一個使用交叉耦合對來提升轉換增益的超寬頻混頻器以及一個提升鎖定頻寬的直接注入鎖定式除頻器。混頻器為一個雙端平衡的混頻器結合交叉耦合對提供負電阻與原本混頻器的負載進行並聯的方式，來提升整體的負載已達到提升轉換增益的效果。在RF與LO輸入端採用內建式的平衡不平衡轉換器使輸出的兩端點達到相位差180度的效果，晶片面積為0.87 × 0.62 mm2。直接注入鎖定式除頻器是採用串聯電感的技術，注入電晶體視為一個混頻器，藉著串連電感的關係，提升混頻器的轉導，以至於提升轉換增益，達到提升鎖定頻寬的效果。其中，交叉耦合對多並聯一組PMOS和NMOS提供負電阻與LC的損耗相互抵消，並聯的效果降低電流使整體電路的功耗降低，晶片面積為0.79 × 0.585 mm2。

關鍵字

CMOS 0.18微米製程 ； 頻率轉換 ； 交叉耦合對 ； 負電阻 ； 平衡不平衡轉換器 ； 串聯電感

並列摘要

This thesis proposes the design and implementation of broadband frequency conversion circuits in CMOS 0.18-μm process. The presented circuits include a conversion gain enhancement ultra-wideband mixer with cross-coupled pair and a locking range enhancement direct injection-locked frequency divider (DILFD). The proposed mixer is a double-balanced mixer (Gilbert cell mixer), which combines the cross-coupled pair to offer negative resistor. The negative resistance parallels with the load of mixer to achieve the effect of the conversion gain boosting. At the RF and LO ports, the Marchand-balun lets output ports have the phase difference of 180 degree. The chip area is 0.87 × 0.62 mm2. The DILFD adopts series-peaking technology to make the injection transistor, as a mixer, increase the locking range. The cross-coupled pair parallels with PMOS and NMOS reduces the power consumption. The chip area is 0.79 × 0.585 mm2.

並列關鍵字

CMOS 0.18-μm process ； frequency conversion ； cross-coupled pair ； negative resistor ； Marchand-balun ； series-peaking

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