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  • 學位論文

寬頻無線電路之設計與分析

Design and Analysis of Broadband Wireless RF Circuits

指導教授 : 呂學士

摘要


隨著科技的演進,無線通訊系統在日常生活中所扮演著不可或缺的腳色。其無線通訊的應用更無所不在,市場也逐漸成長茁壯。因此,在不增加其成本的考量下,如何增加其系統的功能並將商品微小化,是我們感興趣的研究方向。 本篇碩士論文將探討如何實現一具有寬頻特性之無線接收機,也將仔細探討其次電路之設計概念及原理。第一章為本篇碩士論文之簡介,第二章介紹常用之接收機架構,歸納出各種不同接收機之優缺點。第三章將介紹寬頻低雜訊放大器之設計原理,仔細的導証寬頻放大器之雜訊分析。此外,在此章節我們將介紹三種應用於不同系統的超寬頻之低雜訊放大器。第一個寬頻放大器使用0.18um製程,在1.8V之操作電壓下,輸出增益超過14dB,並且最低雜訊低於3dB。其操作頻帶為UWB 2-6GHz。第二個寬頻放大器則是應用於軟體定義無線電系統,晶片則是製作於90nm,其操作電壓為1V,在0.5-10GHz的頻帶下,其增益能達到13dB,雜訊指數更只有2.18dB。第三個放大器利用了主動及被動之帶拒濾波器實現一具有可調變功能之多重notch之寬頻放大器。經由模擬顯示其帶拒功能都達到10dB以上。第四章,將介紹一利用次諧坡開關實現的混波器,此電路也利用一單端轉雙端之設計技巧來提高對雜訊之抵抗能力。 最後,第五章則是利用兩個創新之子電路來實現一軟體無線電之接收機,在1.2V的操作電壓下,其轉換增益能達到20dB以上,線性度以達到-16dBm。其接收機之性能初步達成其系統之需求。

關鍵字

寬頻 無線 電路設計

並列摘要


Along with the technical evolution, the wireless communication system plays an important role in our daily life. The application of using wireless communication is everywhere and its market is also growing gradually. Therefore, the miniaturization and increase the functionality will be the first topic we are interested in. The thesis is not only going to discuss how to implement a wireless receiver with wideband characteristic, but serious discuss the design principle and methodology of the sub-building blocks. Chapter 1 is the introduction of this thesis; chapter 2 introduces the common receiver architectures and summarizes the pros and cons among them. Chapter 3 will introduce the design principle of the wideband low noise amplifier and also derive the noise response. In this chapter, we will discuss three WB-LNAs for different applications. The first WB-LNA is implemented in 0.18um technology, under 1.8VDD, it achieves 14dB of power gain, 3dB of noise figure over the band of 2-6GHz. The second WB-LNA is designed for SDR communication system, the chip is implemented in 90nm CMOS technology, under 1VDD, it achieves 13dB of power gain, 2.18dB of noise figure. The third WB-LNA uses active and passive notch filter, which can realize a reconfigurable multi-notches WB-LNA. From simulation, the result shows that the notching ability is more than 10dB. In chapter 4, we introduce a sub-harmonic mixer which uses a single to differential circuit technique in order to improve noise immunity. In the last chapter, we will implement a Software Defined Radio receiver with two novel sub-circuits. Under 1.2 VDD, the circuit achieves 20dB of conversion gain and -16dBm of IIP3. The receiver basically achieves the requirement of the SDR communication system.

並列關鍵字

wideband wireless circuit design

參考文獻


[1.1] A. Abidi, “Evolution of the Software-Defined Radio (SDR) Receiver”
[2.2] J. Crols and M. S. J. Steyaert, “A Single Chip 900MHz CMOS Receiver Front End with a High Performance Low IF Topology,” IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1492, Dec. 1995.
[3.1] A. Anastassiou and M. J. O. Strutt, “Effect of source lead inductance on the noise figure of a GaAs FET,” Proc. IEEE, vol. 62, no. 3, pp. 406–408, Mar. 1974.
[3.2] D. K. Shaeffer and T. H. Lee, “A 1.5 V, 1.5 GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 745–759, May 1997.
[3.3] H. Samavati, H. R. Rategh, and T. Lee, “A 5-GHz CMOS wireless LAN receiver front end,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp. 765–772, May 2000.

被引用紀錄


Wu, M. S. (2011). 適用於植入式醫療通訊頻段之低功率無線接收機 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2011.10674
Tsou, C. (2010). 低功率頻率調變接收機適用於 315/433/868/915MHz ISM 頻帶 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2010.02403

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