本論文利用CMOS 0.18 μm製程實現了一個應用於UWB的低雜訊放大器。此電路結合LC-ladder filter與負回授電路。利用LC-ladder filter來達到良好的輸入端匹配,利用回授電路使得寬頻增益能較平坦,最後模擬頻寬為3-10 GHz,頻帶內的雜訊指數幾乎都在4 dB以下,最高的增益達到11.3 dB,輸入返回損失都低於-11 dB,輸出返回損失都低於 -12 dB,IIP3為2 dBm,消耗功為18.79 mW。 我們也利用CMOS 0.18 μm 製程實現一個雙頻帶的交叉偶合配對的壓控振盪器。使用切換電感的方法,使單一壓控振盪器達到雙頻帶的振盪頻率。此壓控振盪器使用0.9 V的電壓供應,且3,947及8,002 MHz的相位雜訊在1 MHz偏移時分別為-113.84 dBc/Hz及-110.23 dBc/Hz。此壓控振盪器的核心電路在兩工作頻帶下功率消耗為7.2 mW。
A new ultra-wideband (UWB) CMOS low-noise amplifier (LNA) is proposed, which includes an LC-ladder filter with a resistive shunt-feedback. The LC-ladder filter provides a good input matching and the resistive shunt-feedback renders unconditional stability and flat gain over the passband. The proposed LNA is implemented in 0.18 μm CMOS technology. Simulations show a −3 dB gain bandwidth of 3-10 GHz, the noise figure is less than 4 dB over most of the band, the maximum gain is 11.3 dB, The return loss is lower than −11 dB at the input, and lower than −12 dB at the output, the IIP3 is 2 dBm, and the power consumption is 18.79 mW. A dual-band PMOS cross-coupled pair VCO is designed and fabricated in a 0.18 μm CMOS process. By using the switched-inductor approach, dual band operation is realized using a single VCO. The phase noise at 1 MHz offset is −113.84 dBc/Hz at 3,947 MHz and −110.23 dBc/Hz at 8,002 MHz. The core VCO consumes 7.2 mW in both bands at the supply voltage of 0.9 V.