應用於超寬頻系統之前端電路設計

Design of Front-End Circuit for Ultra-Wideband Applications

嚴聖翔(Sheng-Hsiang Yen)

指導教授 ： 陳淳杰

中原大學/工學院/電子工程研究所/碩士(2007年)

https://doi.org/10.6840/cycu200700525

摘要

在這篇論文中，主要討論如何設計一個應用於超寬頻系統的射頻前端電路，並提出一種結合被動元件組抗匹配與共閘極放大器所設計的新式低功率低雜訊放大器，主動式降頻混頻器，以及兩種不同組合架構的射頻前端電路，並使用TSMC 0.18um RF製程設計與實現。
本篇論文提出兩個低雜訊放大器──混合式共閘極低雜訊放大器以及電容交錯式共閘極低雜訊放大器，其分別應用了兩種增加gm的方法，電感連接式以及電容交錯式，使共閘極放大器的效能提升，並且改善了共閘極放大器的缺點。三階梯型結構被動元件的阻抗匹配可以提供一個寬頻的阻抗匹配，補償增益頻寬。混合式共閘極低雜訊放大器的模擬結果為功率增益15.2dB，雜訊指數 3.8dB，功率消耗為3.24mW；電容交錯式共閘極低雜訊放大器的模擬結果為功率增益16.8dB，雜訊指數 3.2dB，功率消耗為8.75mW。
主動式降頻混頻器可提供轉換增益以及不錯的雜訊效能，本論文設計了一個以柴比雪夫濾波器結構作為寬頻輸入阻抗匹配的雙平衡式混頻器，它的轉換增益為11.6dB，雜訊指數為9.36dB，線性度IIP3 為 -0.67dBm，功率消耗為7.2mW。
最後，針對由低雜訊放大器以及混頻器所組成的射頻前端電路設計了兩組完整電路。第一個電路中，移除阻抗匹配可能會造成一些問題，像是較差的雜訊效能，以及比較低的轉換增益，模擬結果為轉換增益19.5dB，雜訊指數在4GHz時為7.94dB，線性度IIP3為-16.62dBm，消耗功率6.84mW；第二個電路我們在低雜訊放大器以及混頻器中加入匹配電路，模擬結果為轉換增益28.5dB，雜訊指數於4GHz時為6.81dB，線性度IIP3為-14.25dBm，功率消耗為26.76mW。

關鍵字

前端電路 ； 超寬頻系統 ； 低雜訊放大器 ； 混頻器 ； 低功率

並列摘要

In this thesis, we will discuss the design of front-end circuit for ultra-wideband applications. A novel low power LNA which combines common-gate amplifier with reactive matching network, active downconversion mixer, and two front-end circuits are presented. The front-end circuits are designed and implemented in TSMC 0.18um RF process.
Mixed common-gate LNA and cross-coupled common-gate LNA use gm-boosting methods such as inductor-terminated and capacitor cross-coupled to increase power gain, reduce noise figure, and enhance bandwidth. These two gm-boosting methods improve the performance of common-gate LNA. Third-order ladder passive matching networks are placed in circuits skillfully to get wideband matching and enhance bandwidth simultaneously. The simulation results of mixed common-gate LNA include a power gain of 15.2 dB, noise figure of 3.8dB, and power consumption of 3.24mW. The simulation results of cross-coupled common-gate LNA include a power gain of 16.8 dB, noise figure of 3.2dB, and power consumption of 8.75mW.
Active downconversion mixer provides conversion gain and better noise performance. In our design, a double-balanced mixer with reactive input matching network is presented. The input matching network is embedded in the Chebyshev filter structure. The simulated conversion gain and noise figure of wideband double-balanced mixer are 11.6dB and 9.36 dB, input-referred IP3 of -0.67dBm, and power consumption of 7.2mW.
The front-end circuits are combination of LNA and mixer. In the first front-end circuit, removing the input matching network of single-balanced mixer and output matching buffer of mixed common-gate LNA may cause worse noise performance and lower conversion gain. The simulation results include a conversion gain of 19.5 dB, noise figure of 7.94dB at 4GHz, input-referred IP3 of -16.62dBm, and power consumption of 6.84mW. In the second front-end circuit, a matching network connected between LNA and Mixer to improve performance of front-end circuit. The simulation results include a conversion gain of 28.5 dB, noise figure of 6.81dB at 4GHz, input-referred IP3 of -14.25dBm, and power consumption of 26.76mW.

並列關鍵字

LNA ； Mixer ； Low power ； Front-end circuit ； UWB

參考文獻

[1] El-Masry, E. I. and W. Jie. “CMOS micropower universal log-domain biquad,” IEEE Transactions 46(3): 389-392 1999.

[2] FCC, “Final Rule of the Federal Communications Commission, 47 CFR Part 15, Sec. 503,” Federal Register, vol. 67, no. 95, May 2002.

[4] Steve Stroh, Ultra-Wideband Multimedia Unplugged, IEEE Spectrum, September 2003.

[5] Roy, S.; Foerster, J.R.; Somayazulu, V.S.; Leeper, D.G. “Ultrawideband radio design: the promise of high-speed, short-range wireless connectivity,” Proceedings of the IEEE, Vol.92, Iss.2, Feb 2004 Pages: 295- 311.

[6] McCorkle, J. “Ultra wide bandwidth (UWB): gigabit wireless communications for battery operated consumer applications” VLSI Circuits 2005, Digest of Technical Papers. 2005 Symposium on, Vol., Iss., 16-18 June 2005 Pages: 6- 9.