本論文實現了一個應用於ZigBee之低功耗全差動低雜訊放大器。此實現之低雜訊放大器採用共閘極的架構,由於它的輸入匹配及線性度的效能較共源極架構來的好。此低雜訊放大器同時採用轉導提升的技術來降低雜訊指數及提高增益。除此之外,此電路完全無使用電感。此低雜訊放大器在TSMC 0.18 μm CMOS製程下實現,其模擬結果分別為功率增益 10.7 dB、雜訊指數6.5 dB、輸入三階截斷點 –11.7 dBm及1 dB增益壓縮點 –21.5 dBm。在1.8 V的電源供應下功率消耗為 3.6 mW。整個核心電路之佈局面積為0.025 mm2。
In this study, a low power fully differential Low Noise Amplifier was implemented for ZigBee applications. A Common Gate topology was utilized to implemented LNA due to its better input matching and linearity performances than the conventional common-source topology. Meanwhile, the LNA also adopts the well-known gm-boosted techniques to reduce Noise Figure and provides high gain. Moreover, the circuit is fully inductorless. The LNA was simulated in TSMC 0.18 μm CMOS process. The simulated power gain, noise figure, IIP3, and P1dB are 10.7 dB, 6.5 dB, –11.7 dBm, and –21.5 dBm, respectively. The power consumption is 3.6 mW in a 1.8 V power supply. The active layout area is 0.025 mm2.