本論文採用共閘極疊接式低雜訊放大器架構,調整中心頻率使其適用於 802.11a/b/g標準,並利用閘極截止電感補償其轉導值在高頻衰減的現象,讓等效轉導值 Gm的衰減降低。在以TSMC 0.18 μm RF-CMOS 製程技術的模擬結果中,雜訊指數NF介於6~7dB,在S21增益部分峰值達到16.79dB、16.79dB(2.4G/5.2G),在阻抗匹配S11,-18.31dB、-13.53dB(2.4G/5.2G),IP1dB為-21dBm、-23dBm(2.4G/5.2G),IIP3之線性度為-9.9dBm、-11.1dBm(2.4G/5.2G),其晶片面積為1.08mm2 ,而在固定電源供應1.8V下,功率消耗為10.68mW。
In this paper, utilized the Common Gate topology for Low Noise Amplifier. By tuning center frequency apply to 802.11a/b/g protocol. In order to reduce Gm attenuation in high frequency, applying Gate-Terminating Inductor to compensate the degeneration phenomenon. In this study, simulated in TSMC 0.18 μm RF-CMOS standard process, occupies a chip area of 1.08mm2 . The noise figure ranges from 6-7dB. And the gain maximum value |S21| is reach to 16.79dB at 2.4/5.2GHz. Impedance matching |S11| are -18.31dB/-13.53dB at 2.4/5.2GHz. The linearity parameters of 1-dB compression point(IP1dB) are -21dBm/-23dBm at 2.4/5.2GHz,and IIP3 are -9.9dBm/-11.1dBm at 2.4/5.2GHz. The entirely power consumption is 10.68mW at a power supply of 1.8V.