摘要
本論文採用現有的超寬頻低雜訊放大器架構討論雜訊響應的分析。考慮電路當中最主要的雜訊來源，包括電阻熱雜訊和電晶體熱雜訊，並且將這些元件所產生的熱雜訊轉換成雜訊模型。將實現之超寬頻低雜訊放大器電路等效為雜訊模型電路後，得到最簡化的等效雜訊電路，以方便整體電路的雜訊分析。 本論文在 TSMC 0.18μm CMOS 製程下實現，此操作2.7~10.8GHz 的超寬頻低雜訊放大器在1.8V 的電源供應下功率消耗為18mW。其量測結果為：增益範圍(S21)為10.5dB 至13.4dB，雜訊指數範圍(NF)為3dB 至4.64dB，輸入匹配(S11)在-5.3dB 之下，輸出匹配(S22)在-4.79dB 之下，1dB 增益壓縮點(P1dB)為-6dBm，輸入三階截斷點(IIP3)為-2.5dBm。整體核心電路面積為0.419 mm2。
關鍵字
超寬頻、低雜訊放大器、熱雜訊並列摘要
In this paper, based on the existing ultra wideband low noise amplifier architecture discussed noise response. Considering the noise source of the main circuit, including resistance thermal noise and MOS thermal Noise, the noise model from the thermal noise generated by these components. The implementation of ultra wideband low noise amplifier circuit equivalent to the noise model circuit, get the most simple noise circuit, in order to facilitate the circuit noise analysis. The ultra wideband low noise amplifier was implemented in TSMC 0.18μm CMOS process. An ultra wideband 2.7 to 10.8 GHz low noise amplifier and the power consumption is 18mW in a 1.8 V power supply. The measured results are: the gain (S21) ranges from 10.5dB-13.4dB, the noise figure (NF) ranges from 3dB-4.64dB, the Input reflection coefficient (S11) under the -5.3dB, the Output reflection coefficient (S22) under the -4.79dB, the 1db Compression Point (P1dB) is -6dBm, the input third-order intercept point (IIP3) is -2.5dBm. The active layout area is 0.419 mm2.