高遷移率鍺錫金氧半場效電晶體之製備與特性

Fabrication and Characterization of High Mobility GeSn pMOSFETs

黃致皓(Chih-Hao Huang)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201701004

摘要

近代半導體工業依照著莫爾定律不斷地縮小元件尺寸，然而，矽金氧半場效電晶體(MOSFETs)技術已經開始面臨其微縮的極限了。電晶體尺寸微縮進入10奈米節點之後，我們需要高遷移率的通道材料例如鍺以及III-V族材料來提高驅動電流。另外，為了避免短通道效應和減少功耗，新元件結構也正在被開發。由於鍺與矽有很高的相容性，因此目前是非常受注目的材料，也已經被廣泛地探討。為了達到比鍺更高的遷移率，把錫參雜進鍺以合成鍺錫合金是一種能增加載子遷移率的應變工程。
達到高遷移率的鍺錫金氧半電晶體，將面臨的挑戰有：溫度的限制，因為錫在鍺中只有非常低的溶解度，以及與高介電系數材料的整合，包含各種鈍化方法以降低介面缺陷，還有三維電晶體結構的製程以符合未來微縮的需求。在本論文中，我們將演示鍺錫平面場效電晶體以及環繞式閘極場效應電晶體，其中的探討也包含了介面工程、製程整合、遷移率特性、應力響應和雜訊量測。
在本論文中，我們發現10%錫濃度的鍺錫合金溫度限制須在攝氏400度以下以防止應變鬆弛或錫的析出。我們也演示了鍺覆蓋層的薄化製程，以達到最佳化的覆蓋層厚度。鍺錫金氧半電容的介面缺陷密度也利用低溫電導法來量測，以確認鍺覆蓋層的效果。
關於鍺錫平面電晶體的製備，鍺覆蓋層作為鈍化層以減少表面粗糙度散射和庫倫散射。利用低溫原子層沉積氧化鋁與二氧化鋯作為高介電常數材料，也利用快速熱氧化製程作為介面鈍化，並且溫度限制控制在攝氏400度以下以避免錫的析出。製備出的鍺錫金氧半場效電晶體擁有優良的電性：如高達104之開關電流比以及低次臨界擺幅 106 mV/dec。化學氣相沉積成長並以厚度1奈米厚的鍺覆蓋層製備的鍺錫電晶體能擁有高達509 cm2/V-s的電洞遷移率。厚度對遷移率的關係可以用載子在量子井中分布的情形來說明。我們也以外加應力降低載子有效質量，以提升驅動電流。雜訊密度隨著鍺覆蓋層的厚度增加而減少，說明了當載子遠離表面，載子數目擾動與相關遷移率擾動都被抑制了。
關於鍺錫環繞式閘極場效電晶體，硼離子佈植與適當的退火條件可以達到夠低的69 ohm/sq薄片電阻。利用氯氣與溴化氫氣體作非等向性蝕刻去除位於鍺矽介面高缺陷的鍺以形成懸空的奈米線通道，製備出的環繞式閘極場效電晶體可以達到2.3x107的高開關電流比和86mV/dec的低次臨界擺幅。變溫量測方面，在相同過驅電壓下，電流隨著溫度升高而降低，顯示著聲子散射是主要的散射機制。我們也以外加壓縮應力以降低載子有效質量，以提升驅動電流。

關鍵字

鍺錫合金 ； 金氧半電晶體 ； 環繞式閘極場效電晶體 ； 閘極最後製程 ； 高遷移率 ； 表面鈍化 ； 應變 ； 非等向性蝕刻

並列摘要

Semiconductor industry technology has been following the path of scaling trend based on Moore’s law. However, Si MOSFET has come to its scaling limit. For the technology nodes of 10 nm and beyond, high mobility channel material such as Ge and III-V are required to enhance drive current. Also, new device architectures are now been developing to reduce short channel effect and power consumption. With the high compatibility of Ge with Si platform, Ge has become a promising candidate for high mobility channel material and has been widely investigated. To achieve higher mobility than Ge, the incorporation of Sn into Ge to synthesize GeSn alloy is a new way of strain engineering to further boost the mobility.
The primary challenges to achieve high mobility GeSn MOSFET are the thermal budget limit due to low solubility of Sn in Ge, the high-k integration process including various passivation techniques for interface trap reduction and the fabrication of 3D device structure for future scaling need. In this thesis, the fabrication and electrical characterization of germanium-tin based planar and gate-all-around field-effect-transistors are demonstrated. The interface engineering, process integration, mobility characterization, strain response and noise measurement are also investigated.
In this thesis, the GeSn thermal budget is investigated as 400oC for [Sn]=10% to prevent strain relaxation and Sn segregation. The Ge cap thinning process for optimized passivation layer thickness is demonstrated. The interface states densities of GeSn MISCAPs are measured by low temperature conductance method to confirm the effect of Ge cap passivation.
For GeSn planar pMOSFET fabrication, Ge cap is used as passivation layer to reduce surface roughness scattering and Coulomb scattering. Al2O3 and ZrO2 as high-k layer is deposited by atomic layer deposition at low temperature. Rapid thermal oxidation is used as the fast and effective interface passivation with thermal budget under 400oC to prevent Sn segregation.　GeSn pMOSFETs exhibiting excellent transistor characteristic are fabricated. High Ion/Ioff ratio of ~1.1x104, and low subthreshold swing of ~106mV/dec are demonstrated. The high peak hole mobility of 509 cm2/V-s of the CVD-grown GeSn pMOSFETs is obtained using 1nm Ge cap. The cap thickness dependent mobility can be explained by carrier distribution of quantum well structure. The on current is enhanced by external stress due to reduction of effective mass. The normalized noise power density of the GeSn devices decreases with increasing Ge cap thickness, indicating the carrier number fluctuation and correlated mobility fluctuation are suppressed when the holes are away from interface.
For GeSn gate-all-around pMOSFET fabrication, boron implantation with proper annealing condition can achieve low sheet resistance of 69 ohm/sq. Floating GeSn nanowire is form using anisotropic etching with Cl2/HBr gas to etch away the high defective Ge near Ge/Si interface. Favorable on/off ratio of 2.3x108 and low SS of 86mV/dec are fabricated and characterized. The current decreases with the increasing temperature at the same overdrive voltage, indicating phonon scattering is the dominant mechanism. The on current is enhanced by external compressive strain due to reduction of effective mass.

並列關鍵字

Germanium-Tin ； MOSFET ； GAAFET ； Gate-Last Process ； High Mobility ； Surface Passivation ； Strain Response ； Anisotropic etching

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