- 學位論文
應用於高量測頻率範圍CMOS阻抗頻譜量測器之設計
Design of Impedance Measurement Spectroscopy for Wide-frequency Range Applications
摘要
阻抗量測器常見於生物醫療用途上，例如:體脂計、癌細胞檢測…等。而在食品檢驗科技中，如:肉品檢測、牛奶濃度檢測…等，透過阻抗變化而觀察出食品的物質變化。為了能將阻抗量測技術普及化於日常生活中，而不受限於傳統阻抗量測儀的不變攜帶性及高功耗性，故以CMOS晶片來實現以達到微小化之目的。而在量測頻率範圍上，考慮到Fricke model上參數的計算，因此需要高量測頻率範圍以滿足。此外待測物的阻抗大小範圍、待測物的阻抗相位範圍、解析度考量、雜訊…等皆需納入設計考量。本論文實作並量測兩個不同架構的CMOS阻抗量測器，第一個架構為使用傳統的振幅/相位量測系統並改良之，以積分器取代耗費巨大面積的低通濾波器，並改善積分器在低量測頻率時易飽和之問題。雖然此架構可以達到高精確度之阻抗量測，但其前端電路如:正弦波電流產生器、儀表放大器…等其功耗皆會隨所需量測頻率而增加。而第二個架構，採用方波電流同步偵測 (synchronous detection)之架構，可大大降低前端電路之功耗，並以諧波錯誤補償方法來降低方波電流所帶來之奇次諧波錯誤項。 此兩個電路皆實作於台積電 0.18微米製程，第一個晶片面積為 2.16平方毫米，在1.8伏特電源下消耗3.4微瓦，在阻抗振幅與相位的精準度上分別為 1.46 %/1.02°。第二個晶片面積為 3.4平方毫米，在 1.8伏特電源下消耗 0.29 微瓦，在阻抗實部與虛部的精準度上分別為 2.88/2.4 %。
關鍵字
阻抗量測並列摘要
The impedance measurement analyzer is commonly used in biomedical applications, such as body fat monitor, cancer cell detection…etc. The impedance measurement technique also appears in the testing method of the food industry, such as meat quality, the concentration of milk…etc. The variation in impedance is observed to obtain the information about the variation of substance. To generalize the impedance measurement technique in daily life, and unrestricted by large-size and large power-consumption of traditional impedance analyzer. Therefore, the CMOS process is employed to miniaturize the analyzer. By considering the extraction of the parameters in the Fricke model, the wide measurement frequency range is required. The range of the device under test (DUT) impedance magnitude and phase, noise…etc. are all considered in circuit design. Two circuit architecture of the impedance measurement analyzer are implemented and verified in this thesis. Based on the traditional magnitude/phase measurement system, the first chip replaces the area-consumed LPF with integrator, and improves the saturation problem of the integrator in low measurement frequency. However, the front-end circuits such as VCCS, IA consume large power as measurement frequency increases. Therefore, the second chip utilizes the squared-wave based synchronous detection system to decrease the power-consumption of the front-end circuit. The odd harmonic errors introduced by square-wave current injection are eliminated by the harmonic error cancellation method. The two impedance measurement analyzer chips are fabricated in the 0.18-um TSMC CMOS process. The first chip occupies 2.16 mm^2 chip area and consumes 3.9 mW from a 1.8 V supply. The error of the magnitude measurement and phase measurement are 1.46 %/1.02° respectively. The second chip occupies 3.4 mm^2 chip area and consumes 0.29 mW from a 1.8 V supply. The error of the real measurement and imaginary measurement are 2.88/2.4 % respectively.
並列關鍵字
Impedance measurement參考文獻
延伸閱讀
- Wu, C. R. (2006). 適用於多頻段/多規格通訊系統之CMOS無線接收機電路設計與實現 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2006.02017
- Yen, H. D. (2014). CMOS 射頻/毫米波電路設計與可靠性分析之研究 [doctoral dissertation, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-2912201413560553
- 林書毓（2009）。利用CMOS製程設計製作電磁能隙結構傳輸線與其寬頻特性量測〔碩士論文，元智大學〕。華藝線上圖書館。https://doi.org/10.6838/YZU.2009.00319
- 黃建文（2015）。Simulation of Piezoelectric Impedance-based Load Measurement Devices using Impedance〔碩士論文，國立交通大學〕。華藝線上圖書館。https://doi.org/10.6842/NCTU.2015.00078
- 黃鳴鋒（2012）。Microcontroller-based high-accuracy impedance measurement system〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2012.11028