以Verilog轉換SystemC完成嵌入式處理器之功率預測

近年來因為可攜式的電子產品需求量大增，大眾對於電池的續航力的要求也越來越高，因而功率消耗的問題成為受人曯目的重要議題。使用Verilog HDL來開發硬體時，可以從中得到功率消耗的資訊，但是卻相當的耗費時間。考慮到系統整體的運作，包含硬體與軟體部分的耗能評估及管理，希望能有更快速的機制。若能從暫存器傳輸層級提升至較高層級的硬體描述語言SystemC，並且將耗能的資訊加入於SystemC之中，便可以有效率地達到耗能評估及管理的目的。在本文中，我們選用了一個開放原始碼，是由Sun UltralSPARC T1所延伸出的Simply RISC處理器，並提出基於Verilog HDL轉換成SystemC的功率消耗模組。隨後在以模擬器執行軟體的過程中，便可以提供此SystemC所模擬之硬體模組的功率耗費情形，而不必使用原有的Verilog HDL模組，因此效能可以達到15倍之多。由實驗的結果得知此功耗模組相較於以Verilog HDL原始碼經由電子設計自動化工具所量測的誤差值在3%以下，因此使用較高層級的硬體描述語言來進行耗能的評估也能有很好的準確性。

關鍵字

Verilog HDL ； SystemC ；轉換；功率預測

並列摘要

With the growing demand of the portable devices in recent years, battery life and power consumption have become important in the design of embedded systems. While the Verilog HDL is popular for hardware engineers to design chips, it is very time-consuming to using Verilog HDL for power analysis. One would prefer to use a higher level system design language, e.g. SystemC, to evaluate and model the power consumption of a system in an early design stage. In this thesis, we　choose to study Simply RISC, an open source chip design, based on Sun UltraSPARC T1, and proposed a power estimation scheme based on Verilog-to-SystemC conversion. Given a program, the scheme reports the information of power consumption for the converted SystemC module, with up to the 15X speedup over Verilog HDL-based simulation, while the estimated power is within 1.53% of the result from a Verilog HDL simulation tool.

並列關鍵字

Verilog HDL ； SystemC ； conversion ； power estimation

參考文獻

[4] Panda, P.R., "SystemC: a modeling platform supporting multiple design abstractions", in Proceedings of the 14th international symposium on Systems synthesis, October 2001

[7] Talarico, C., Rozenblit, J.W., Malhotra, V., and Stritter, A., "A New Framework for Power Estimation of Embedded Systems", Computer, vol. 38, no. 2, 2005.

[17] Srivastava, A.V., Verilog-to-C-Compiler: Simulator Generator, Indian Institute of Technology Kanpur, 2007

[18] Extensible Markup Language, http://www.w3.org/XML/

[19] XSL Transformations Version 1.0, http://www.w3.org/TR/xslt

國際替代計量

以Verilog轉換SystemC完成嵌入式處理器之功率預測

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