嵌入式計算機系統效能與功率分析之模擬環境設計

由於消費性電子產品的高度需求帶動了嵌入式系統的蓬勃發展，在快速導入市場的壓力之下，系統設計者在早期開發階段對於系統效能評估以及預測顯得特別重要。另外在這些電子產品中，可攜式裝置佔了大部分，系統功率消耗也成為了設計時期必須納入考量的因素。因此在本論文中，要探討的主題即為系統層級的效能及功率評估方法，透過評測分析應用程式的行為建立而成的應用程式模型及功率模型，放入根據目標平台參數所建立的硬體結構平台，進行交互模擬，提供一個快速的評估環境。我們使用Mibench作為目標應用程式，在效能部分，使用Cycle-Accurate 的ARM SoC Designer Simulator當作比較對象；功率部份，我們著重在記憶體系統的功耗，並且使用DRAMsim進行驗證。從實驗結果得知，模擬速度平均約有15倍至25倍的加速，效能評估誤差率在15%以下，功率評估誤差則在6%以下。從結果來看模擬的速度有顯著的提升，未來將致力於更精準的應用程式及硬體結構模型建構，以及加入其他功率消耗元件。

關鍵字

行為模擬；效能分析；功率評估

並列摘要

Due to the high demand of the consumer electronics, embedded systems generally have short product design cycles. To shorten the time to market, system designers need a way to quickly validate the performance for the entire system in the early design stage. For battery-powered devices, power consumption is also critical issue. Thus, we propose a simulation framework to estimate the performance and power consumption of memory system jointly using behavioral models. Our results showed that our simulation scheme reduced simulation time by up to 25X , compared to the ARM SoC Designer, a cycle-accurate simulator, while the error was controlled under 0.67%, 8.16% and 11.78% for single-core, dual-core and 4-core systems respectively. For the power consumption of the memory system, the error was under 6%. Thus, our framework provides a significant improvement of simulation speed over the traditional method and still delivers reasonable accuracy for joint performance and power consumption evaluation.

並列關鍵字

behavioral simulation ； performance analysis ； power estimation

參考文獻

[3] Sungjoo, Y., Iuliana, B., Aimen, B., Yanick, P., and Ahmed, A.J., "Building Fast and Accurate Sw Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer", in Proceedings of the conference on Design, Automation and Test in Europe - Volume 1, 2003

[4] In-Cheol, P., Sehyeon, K., and Yongseok, Y., "Fast Cycle-Accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation", in Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, 2003

[5] A.Snavely, L.Carrington, and Wolter, N., "Modeling Application Performance by Convolving Machine Signatures with Application Profiles", Proc. IEEE Workshop on Workload Characterization, 2001.

[13] Paul, L., "High-Level Power Estimation", in Proceedings of the 1996 international symposium on Low power electronics and design, 1996

[14] Tony, D.G., Frank, V., J, and rg, H., "Instruction-Based System-Level Power Evaluation of System-on-a-Chip Peripheral Cores", in Proceedings of the 13th international symposium on System synthesis, 2000

國際替代計量

嵌入式計算機系統效能與功率分析之模擬環境設計

主題瀏覽