加入鍺錫磊晶層之鎳/鍺蕭基二極體的接觸電性研究

Electrical characteristics of Ni/n-Ge Schottky diode with a n-GeSn epitaxial layer

鄭禮賢(Li-Sian Jheng)

指導教授 ： 鄭鴻祥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2017年)

https://doi.org/10.6342/NTU201701027

摘要

人們自開始使用矽作為金氧半場效電金體的主要半導體材料算起，已經有將近五十幾年的時間了，隨著製程技術不斷的在進步，電晶體的尺寸也成功的微縮，可是如果照著這個趨勢持續發展下去的話，它遲早都會面臨到它的物理極限，導致電晶體的效能成長開始出現停滯，所以我們勢必要思考其他的方法，讓電晶體的效能可以繼續的向上提升，這個時候，尋找其他可以替代矽的半導體材料，就是一種可行的方法之一，而我們首先想到的就是鍺這種材料。由於鍺跟矽都是四族元素的一種，所以可以輕易的與傳統的矽製程相互兼容，最重要的是鍺的電子以及電洞飄移率皆優於傳統的矽材料，這也讓它被認為十分有機會可以取代矽，成為下一個世代的主要半導體材料。但是鍺本身有非常嚴重的費米能階釘扎效應存在，這會導致鍺跟大部分的金屬形成接觸後，在接面都產生一個很高的蕭基位障，這也造成鍺電晶體的效能往往都不如預期，所以為了要實現鍺在高效能元件的應用，以及降低元件本身的功率消耗，我們勢必要想辦法來降低鍺接面的蕭基位障高度。
在本篇論文中，我們在鎳以及n型鍺基板之間加入一層n型的鍺錫磊晶層，並且透過從文獻上參考的分析方法，對加入鍺錫以及沒有加鍺錫的兩種樣品進行了電性分析，而從實驗的結果我們觀察到加入鍺錫的樣品比起沒有加鍺錫的樣品，有著更低的理想因子以及蕭基位障，蕭基位障高度從0.557eV下降到了0.523eV，不過串聯電阻也會相對的因為多加入一層材料而向上提升。
再來我們也透過變溫的電性量測，觀察到了一些沒有辦法使用熱離子放射理論來解釋的現象，而經過參考一些外部文獻，我們了解到了蕭基位障事實上會以不均勻分布的方式存在於金屬跟半導體的界面，經過分析的結果我們也得到鎳跟鍺錫的接面會比鎳跟鍺的接面要來的平坦。
最後我們嘗試利用預退火(在蒸鍍鎳電極之前的退火)的方式使鍺錫磊 晶層中的錫，偏析至靠近表面的地方，使得靠近表面的鍺錫所含有的錫的 比例增加，這樣可以進一步的讓接面的能隙寬度降低，蕭基位障高度也會隨之減少。

關鍵字

鍺錫磊晶層 ； 接觸 ； 蕭基位障高度 ； 低溫量測 ； 錫的偏析

並列摘要

It have been passing about fifty years from using Si to be the major semiconductor materials of the metal-oxide-semiconductor field effect transistors (MOSTETs). With the progress of nano-fabrication technology, transistors have been successfully scaled done. But the continued scaling will be the problem due to several physical and technical limitations, results in the progress retardation of efficiency of transistors. We need to find another way to keep the efficiency growing, than using the other materials to substitute Si would be a probable way. Because Ge and Si are both belong to group IV material, it can be easily integrated on tradition fabrication of Si. Moreover, the both electron and hole mobility of Ge are higher than Si. so it is considered the promising candidate to replace Si to be the next-generation semiconductor material.
However, there exists a serious fermi-level pinning effect in a metal/n-Ge contact system, resulting in high power consumption because of a higher Schottky barrier height between metal/n-Ge interface. To solve the question of power consumption of Ge-based devices, reducing the Schottky barrier height of metal/n-Ge interface is important.
In this thesis, a n-GeSn epitaxial layer was inserted into Ni/n-Ge interface, using the analysis method reported on reference, the electrical characteristics of the Ni/n-GeSn/n-Ge and Ni/n-Ge samples were analyzed. The experimental result shows that the Schottky barrier height of sample with GeSn epitaxial layer is lower than the sample without GeSn layer between Ni/Ge interface, Schottky barrier height reduced from 0.557eV to 0.523eV. However, the series resistance was increased due to the added GeSn layer.
We measure the electrical characteristics of our contact sample at lower temperature, the results show that the behavior of Schottky diode deviate from pure thermionic emission theory with decreasing temperature. By searching the related reference we realize the inhomogeneity of Schottky barrier height between metal/semiconductor interface, and found that the interface of Ni/GeSn is more flatter than Ni/Ge.
We use the pre-annealing(annealing before the metal contacts deposition) treatment for our N922 sample, which can drive the Sn atoms to the surface of GeSn layer, forming a thin GeSn layer with a Sn composition larger than the underlying GeSn film. It can further decrease the band gap of contact GeSn layer, Schottky barrier height will be reduced.

並列關鍵字

GeSn epitaxial layer ； Contacts ； Schottky barrier height ； Low temperature measurement ； Sn segregation.

參考文獻

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