於可動態局部重組邏輯閘陣列上考量漏電功耗之工作排程

Leakage-Aware Task Scheduling for Partially Dynamic Reconfigurable FPGAs

李奇峰(Chi-Feng Li)

指導教授 ： 楊佳玲

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.01429

摘要

隨著製程技術進步到90奈米以下，在追求高效能和低功耗的嵌入式系統上使用可程式化邏輯閘陣列(Field-Programmable Gate Array, FPGA)時，降低漏電功耗(Leakage power)已經變成一項重要的議題。本篇論文著重於有睡眠電晶體(Sleep transistor)及預先載入機制(Prefetch technique)的可動態局部重組態可程式化邏輯閘陣列(Partially Dynamically Reconfigurable FPGAs)上，漏電功耗的問題。有可預先載入的機制下，一件工作可被切分為兩部分，一是用於重組局部FPGA的重組部分，另一個是執行工作功能的執行部分。我們專注於消除因重組(Reconfiguration)及任務執行(Task execution)之間的閒置延遲，而造成的虛耗漏電功耗(Leakage waste)。
我們提出依據整數線性規劃的方式求出最佳解以及一個不降低效能且減少虛耗漏電功耗的兩階段(Two-stage)排程/擺置法。第一階段，我們使用能有效縮短總執行時間的效能導向(Performance-driven)排程，產生符合單重組單元(Single Reconfiguration)和其他資源限制的正確擺置。第二個階段，我們使用擺置後(Post-placement)考量虛耗漏電功耗的排程演算法，用於改善前一個效能導向排程所產生的擺置，進而得到不犧牲效能且具有虛耗漏電功耗最小化的擺置。
在作用於真實與合成設計上所得的結果中，我們的兩階段演算法可以在較少的電腦計算時間下，得到接近由整數線性規劃表述所得出的最佳化虛耗漏電功耗。

關鍵字

可程式化邏輯閘陣列 ； 擺置 ； 漏電功耗 ； 排程 ； 效能

並列摘要

As technology advances to 90nm and below, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes imperative for adopting FPGAs in both high performance and low power embedded computing devices. In this paper, we address the leakage issue of partially dynamical reconfigurable FPGA architectures with sleep transistors embedded into FPGA fabric and the prefetch technique. Under the prefetch technique, a task is divided into the reconfiguration component that reconfigures a portion of FPGA for execution and execution component that
performs its functionality. We focus on eliminating leakage waste due to the delay between reconfiguration and execution points. We propose an optimal algorithm based on integer linear programming (ILP) and a two-stage task scheduling algorithm to reduce leakage power without sacrificing performance. In the first stage, we use a performance-driven task scheduler that minimizes the schedule length of an application to generate a feasible placement considering the single reconfiguration
and resource constraints imposed by the target system. In the second stage, we perform post-placement leakage-aware task scheduling to minimize the leakage waste provided that the schedule length obtained by the performance-driven task
scheduler is not increased. Experimental results on real and synthetic designs show that our two-stage algorithm can obtain near-optimal solution with less CPU time compared with the ILP formulation.

並列關鍵字

FPGA, Placement, Leakage, Scheduling, Performance

參考文獻

[1] J. Anderson and F. Najm. Active Leakage Power Optimization for FPGAs.

IEEE Transactions on Computer-Aided Design (TCAD), 25(3):423–437, 2006.

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[3] S. Banerjee, E. Bozorgzadeh, and N. Dutt. Physically-Aware HW-SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration.

[4] R. P. Bharadwaj, R. Konar, P. T. Balsara, and D. Bhatia. Exploiting Temporal Idleness to Reduce Leakage Power in Programmable Architectures. In Proceedings of the 10th Asia and South Pacific Design Automation Conference