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  • 學位論文

以CMOS 0.18微米製程實現400 MHz植入式醫療通訊系統之數位校正超再生接收機

A 400-MHz Super-Regenerative Receiver with Digital Calibration for MICS Applications in 0.18-μm CMOS Process

指導教授 : 林宗賢

摘要


無資料

關鍵字

超再生接收機

並列摘要


In this work, we adopt the super-regenerative receiver to implement the receiver for the Medical Implant Communications Service (MICS) applications. The receiver is designed to demodulate the on-off keying signal. The architecture is simple and consumes low power. The proposed topology incorporates digital circuits to generate the quench signal on chip. In addition, an open-loop frequency calibration loop is proposed to adjust the digitally-controlled oscillator frequency to the MICS band. Although a phase-locked loop can also lock the oscillator frequency and achieve precise frequency calibration, its locking time is long. This proposed frequency calibration loop can adjust the oscillator frequency in 4 μs; thus, it saves energy consumption. Fabricated in a 0.18-μm CMOS process, the measurement results show the proposed topology dissipates 3.5 mA from a 1.5-V supply. The total calibration time is less than 20 μs. The receiver has a sensitivity of -83 dBm and a maximum data rate of 1 Mbps. The chip area of the fully-integrated super-regenerative receiver is 1.47 mm X 1.46 mm including pads. The core area is 0.9 mm X 1 mm.

並列關鍵字

super-regenerative receiver

參考文獻


[1] Federal Communications Commission:
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[6] A. Vouilloz, M. Declercq, and C. Deollain, “A low-power CMOS super-regenerative receiver at 1 GHz,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp.440-451, Mar. 2001.
[7] J.-Y. Chen, M. P. Flynn, and J. P. Hayes, “A fully integrated auto-calibrated super-regenerative receiver in 0.13-μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, pp. 1976-1985, Sept. 2007.
[8] J.-Y. Chen, M. P. Flynn, and J. P. Hayes, “A fully integrated auto-calibrated super-regenerative receiver,” IEEE ISSCC Dig. Tech. Papers, pp.376-377, 2006.

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