一個0.016mm2使用電容倍增技術之次取樣鎖相迴路

A 0.016mm2 Sub-Sampling PLL with Capacitor Multiplier Technique

張佳瑋(Chia-Wei Chang)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201901760

摘要

隨著物聯網技術的進步以及普及，有著多樣化的應用及產品，而串連起他們的便是無線傳輸，因此，晶片內的收發器便扮演著不可或缺的色。在大多數的收發器內，頻率合成器提供其傳輸訊號的參考頻率 ，而頻率合成器則為鎖相迴路的其中一種應用。然而，鎖相迴路佔據收發器電路內大量的面積造成晶片面積也較大。對於小體積的電子產品來說，其產品的體積會受到晶片大小的限制，例如:穿戴式裝置。而對於生產來說，因為晶片面積較大，所以同一片晶圓能製成的晶片數量相對較少，需花費較多的成本也會是現實上的重要考量之一。本篇論文中將針對上述之議題提出架構上的討論及改善的設計方法。我們提出了一個基於電容倍增迴路濾波器之單一電荷泵次取樣鎖相迴路 ，其操作頻率為2.4GHz。晶片採用TSMC 90nm標準CMOS製程實現，晶片面積和核心面積分別0.3975mm2和0.016mm2。在操作頻率為2.4GHz時，位移1MHz的相位雜訊為-94 dBc/Hz，積分範圍從10kHz到10MHz的方均根抖動量為 3.43ps，參考突波為-52.34dBc，功率消耗為4.33mW。由於迴路濾波器電容在採用環形震盪器的鎖相迴路中佔據大量面積我們將採用電容倍增技術來縮小面積，並根據迴路濾波器帶通的特性以及適當的設計，濾除此技術引入之雜訊，再與傳統二階迴路濾波器之阻抗及相位做比較，來證明其與傳統二階迴路濾波器為等效的操作。針對相位雜訊的問題，我們採用了次取樣鎖定迴路的技術來抑制頻帶內的相位雜訊和抖動。並使用緩衝器隔絕次取樣相位偵測器的副作用，藉此抑制參考突波。除此之外，使用邏輯電路來取代頻率鎖定迴路之電荷泵，整個鎖相迴路內僅使用了一個電荷泵來減少面積消耗。

關鍵字

次取樣鎖相迴路 ； 電容倍增技術 ； 單一充電泵

並列摘要

With the progress and popularization of Internet of things (IoTs), there are various applications and products. Therefore, transceivers acting as the bridges between applications and products in a chip are indispensable. In most transceivers, a frequency synthesizer which is one of the applications of the phase-locked loop provides the reference frequency for signal transmission. However, the phase-locked loop occupies large area compared with the whole transceiver chip. For small electronic products such as wearable devices, there is a limitation to their volume due to the size of the chip. For the production of wafer, the number of chips is less than the production with a small area phase-locked loop. In other words, it costs much to produce.In this thesis, we propose an improved solution to the above topics. The proposed circuit is a capacitor multiplier loop filter-based sub-sampling phased-locked loop with a single charge pump at 2.4GHz operation frequency. The chip is fabricated in TSMC 90nm Standard CMOS Technology. The chip area and active core area are 0.3975mm2 and 0.016mm2, respectively. At the output clock of 2.4GHz, the measured spur level at 37.5MHz away from the 2.4GHz clock output is -52.34dBc. The measured phase noise at 1MHz offset is -94dBc/Hz and the measured RMS jitter integrated from 10kHz to 10MHz is 3.43ps. The power consumption of the fabricated circuit is 4.33mW. The capacitor in the loop filter dominates the chip area in a ring oscillator phase-locked loop. Therefore, the capacitor multiplier technique is proposed to reduce the area of the capacitor. Based on the band-pass characteristic of the loop filter and careful design, the noise produced by this technique can be filtered. Furthermore, the impedance of the loop filter can be simulated to make sure that the behavior of the loop filter with this technique is the same as a traditional second-order loop filter. The sub-sampling technique is adopted to suppress the in-band phase noise of the phase-locked loop. The reference spur caused by the side effects of the sub-sampling phase detector is suppressed by utilizing isolation buffers. Furthermore, the charge pump in the frequency-locked loop is replaced with logic circuits, that is, the whole circuit only possesses a charge pump. By means of this method, the area of the chip can be reduced.

並列關鍵字

Sub-Sampling Phase-Locked Loop ； Capacitor Multiplier ； Single Charge Pump

參考文獻

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