三維記憶體封裝模型化與信號及電源完整性設計

行動通訊裝置近幾年來進步迅速，且朝向輕薄省電且高頻寬的趨勢發展。為了達成此目的，透過三維整合的寬頻輸出入架構與第四代雙倍資料率同步隨機存取記憶體成為最熱門的技術。本論文著重於兩大行動記憶體的三維整合連結—穿矽連通柱與晶圓級構裝。首先，為了分析穿矽連通柱與矽基板間的基板雜訊耦合，建立了由電阻與電容組成的等效電路，模型中的電阻與電容皆滿足相同的拉普拉斯方程式但具有不同的邊界條件，透過計算不同介質的電容結構可以得到模型中的元件值，並藉由設計接地防護圈結構來驗證其對基板雜訊耦合的抑制效果。接著，為了處理寬頻輸出入架構晶片間大量穿矽連通柱的問題，本論文基於二維傅立葉轉換提出一種簡化且有效率的週期性穿矽連通柱陣列模型。透過此簡化模型更可以進一步計算寬頻輸出入架構中，降低信號串音的接地穿矽連通柱的位置與數量。對於另一種三維整合構裝技術，晶圓級構裝，本論文提出一種應用於第四代雙倍資料率同步隨機存取記憶體的新式雙層重新分配層設計，這種新穎的電源接地網格式佈局可以有效提升電源完整度。此外，為了處理製程微縮產生的效應，本文提出二階串聯RLC等效電路與規一化阻抗，並利用適當設計重新分配層的尺寸優化眼圖，使第四代雙倍資料率同步隨機存取記憶體於2微米的晶圓級構裝製程中，可正常運作於4266 Mbps的速度。最後，除了訊號及電源完整度外，本論文也探討電磁干擾的問題。對於構裝基板中電源接地層的板邊輻射現象，本論文透過模態分析分離不同模態的輻射機制。並設計不同尺寸的接地連通柱以實現不同程度的板邊輻射抑制。

關鍵字

行動記憶體；三維整合；穿矽連通柱陣列；基板雜訊；晶圓級構裝；眼圖；信號/電源完整度；重新分配層；板邊輻射；短路連通柱

並列摘要

Mobile devices develop rapidly in recent few years, with the trends of the slim, low-power, and high bandwidth features. The three-dimensional integration such as Wide-I/O and LPDDR4 DRAM become the most popular technologies. This dissertation focuses on the interconnects of two popular mobile memories, through-silicon-via (TSV) and wafer-level packaging (WLP). To begin with, the equivalent model consisting of resistors and capacitors is established in order to analyze the substrate noise coupling between TSVs and silicon substrate. It deserves notice that the resistors and capacitors in the equivalent model satisfy the same Laplace equation but with different boundary conditions, and thus the resistance model can be judiciously solved from the capacitance computations which are readily available from commercial software. Based on that, the guard ring design is also employed to validate the accuracy of the present model and its suppressing effect on the substrate noise. Next, for dealing with large numbers of TSVs between Wide-I/O chips, this dissertation proposed a method of creating a simplified and efficient equivalent model for periodic TSV array based on the two-dimensional Fourier transform. The simplified model is also used to effectively access the position and number of dummy ground TSV to reduce the crosstalk between signals in Wide-I/O architecture. As for the WLP, this dissertation proposed a novel two-layer re-distributed layer (RDL) design in LPDDR4 applications by utilizing a novel power/ground meshed layout for superior power integrity performance. Besides, in order to handle the effect of process shrinkage, the 2nd order series RLC circuit and normalized resistance is proposed. By adjusting the cross-sectional structure of RDL properly, the eye-diagram can be optimized and LPDDR4 memory can work well at 4266 Mbps on 2 μm WLP. The last, in addition to signal and power integrity, the dissertation also addressed the electromagnetic interference issues. It employs the mode analysis to separate the radiation mechanisms of different modes for edge radiation of power/ground plane in multi-layer package. The size of shorting via is also designed to implement the different level suppression of edge radiation.

並列關鍵字

Mobile memory ； three-dimensional integration ； through-silicon-via ； substrate noise ； wafer-level packaging ； eye-diagram ； signal/power integrity ； re-distribution layer ； edge radiation ； shorting via

參考文獻

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三維記憶體封裝模型化與信號及電源完整性設計

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