應用於生醫系統之低功率類比數位轉換器與超級再生式接收機

Low Power Analog-to-Digital Converter and Super-Regenerative Receiver for Bio-Medical Applications

張祐匡(You-Kuang Chang)

指導教授 ： 汪重光

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.01704

摘要

隨著生物醫學微機電系統(Bio-MEMS)與無線網路技術的興起，可植入性生物醫學系統變成非常熱門的一項新興研究領域。在此研究中，如何降低整個系統的功率消耗儼然成為首要的挑戰。電路所消耗的能量是以熱的形式散逸在空氣中並且會提高晶片周遭環境的溫度，所以將系統置入人體內，萬一晶片的功率消耗太大，將會提高體內局部的溫度進而對神經或器官造成嚴重的損傷。在本論文中，將提出應用在此領域的低功率逐步逼近式類比數位轉換器(SAR ADC)與超級再生式接收機(Super-Regenerative Receiver)。
在八位元類比數位轉換器方面，提出一個省電電容切換次序來降低消耗在電容陣列之能量來達到低功率操作的目的。比起傳統的電容切換次序，新提出的方法可以有效降低56%的能量消耗。此類比數位轉換器採用0.18-μm CMOS的製程，操作電壓為1伏特，在500KS/s的取樣頻率下所量測到的訊息噪音和失真比(SNDR)為46.92 dB，而功率消耗僅為7.75-μW。
在本論文後半部分也提出一個操作在915MHz ISM頻帶的超級再生式接收機。超級再生式震盪器，同時也是接收機的核心，被一個五位元的數位類比轉換器所控制，因此可以很準確地定義接收機的選擇率(selectivity)。此外，將電晶體操作在次臨界區可以降低接收機所需要的功率消耗。模擬結果顯示出此接收機在0.18-μm CMOS的製程和1伏特的電壓下，可以達到-90dBm的靈敏度(sensitivity)及1Mbps的位元傳輸率，功率消耗為0.8mW。

關鍵字

類比數位轉換器 ； 超級再生式接收機

並列摘要

As the emerging of the bio-MEMS and wireless technology, the implantable bio-medical system becomes a popular research topic. The primary challenge is how to reduce power consumption of the system. Low power operation is essential for any implanted bio-medical system as the heat spread by the circuits will increase local temperature which may damage our organs and neurons. This thesis presents a low power successive-approximation-register analog-to-digital converter (SAR ADC) and a low power super-regenerative receiver for bio-medical applications.
In this 8-bit SAR ADC, an energy-saving switching sequence technique is proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 56% compared to a conventional switching sequence. The measured signal-to-noise-and-distortion ratios of the ADC is 46.92 dB at 500KS/s sampling rate with an ultra-low power consumption of only 7.75-μW from a 1-V supply voltage. The ADC is fabricated in a 0.18-μm CMOS technology.
A low-power super-regenerative receiver for 915MHz ISM band is also presented. The super-regenerative oscillator which is the core of the receiver is quenched by a 5-bit DAC and therefore the selectivity of the receiver can be controlled precisely. Furthermore, operating the MOS in sub-threshold region lowers the power consumption of the receiver. The simulation results show that the receiver consumes 0.8mW for a sensitivity of -90dBm and data rate of 1Mbps at 1-V supply voltage in a 0.18-μm CMOS technology.

並列關鍵字

SAR ADC ； Super-Regenerative Receiver

參考文獻

[1.1] C.–H. Chen, et al., “AWireless Bio-MEMS for C-Reactive Protein Detection Based on Nanomechanics ,” ISSCC Dig. Tech. Papers, pp. 376-377, Feb. 2006.

[2.1] S. Mortezapour and E. Lee, “A 1-V 8-bit successive approximation ADC in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, no. 4, pp. 642-646, Apr. 2000.

[2.2] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, “A 0.5-V 1-μW Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, July 2003.

[2.3] M. Scott, B. Boser, and K. Pister, “An Ultra Low-Energy ADC for Smart Dust,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, July 2003.

[2.4] N. Verma and A. Chandrakasan, “A 25μW 100kS/s 12b ADC for Wireless Micro-Sensor Applications,” ISSCC Dig. Tech. Papers, pp. 222-223, Feb. 2006.