以遮蔽式蒸鍍及硝酸氧化技術低溫製備高介電係數氧化鋁閘極介電層

本論文主要研究在低溫製程條件下的高介電係數氧化鋁閘極介電層之電特性。為了阻止鋁原子穿過二氧化矽中間介電層產生反應，在文章中提出兩種有效的方法。本實驗的氧化鋁製備是先將蒸鍍好的超薄鋁浸泡在硝酸中進行氧化，再以交直流電場補償的方法在去離子水中改善其表面特性。而p型矽基板與氧化鋁之間的中間介電層二氧化矽是在純水中以陽極氧化的方法生長。第一個實驗我們在一次氧化鋁製備以及連續兩次氧化鋁製備疊層的樣本中做對照比較。藉由穿透式電子顯微鏡的剖面解析，發現室溫條件下以陽極氧化生長的二氧化鋁無法阻擋鋁原子鑽入與其反應，且其閘極漏電流相當大。然而在經過連續兩次氧化鋁製備後，閘極漏電流大幅下降了約有10的10次方倍之多，也具備良好的電容電壓特性曲線。我們推斷由於第一層的氧化鋁可以有效阻止鋁原子穿透效應，而使再疊上去的氧化鋁可以順利地成長，因此展現出相當不錯的電特性及穩定度。其在高電場環境下的載子行為可以F-N穿隧機制解釋，低電場下的載子行為則符合P-F穿隧理論。接下來的實驗，我們將以陽極氧化生長的二氧化鋁置於380 ℃的氮氣中進行熱退火，此舉可有效去除氫或其他帶電的離子。經過熱退火，電容及電流對電壓的特性曲線皆有顯著的改善，說明了中間介電層修護的必要性。相較於未經過二氧化矽熱退火的樣本而言，經過熱退火可使閘極漏電流降低100至1000倍。以定電流對樣本施加應力觀察其電壓波動的行為，發現界面電荷陷阱數量也因為熱退火而減少。

關鍵字

高介電係數氧化層；低溫製程；硝酸氧化

並列摘要

In this work, the electrical characteristics of Al2O3 high-k gate dielectric prepared under low thermal budget environment are investigated. Two approaches for preventing alloy spiking through effect are presented. Al2O3 gate dielectric was prepared by ultra-thin aluminum film with nitric acid (HNO3) oxidation, and followed by DAC-ANO compensation. The interfacial SiO2 was grown by anodization in D.I water. At first, we made two samples, one with once Al2O3 film fabrication, and the other with twice. The TEM picture reveals that the initial SiO2 grown under room-temperature by anodization failed to block the Aluminum atoms from spiking through. Results show that the sample with only once Al2O3 film fabrication could poorly reduce the leakage current. On the other hand, twice Al2O3 film fabrications made a big improvement in gate leakage current suppression, about ten orders difference in maximum value between the two samples. The C-V behaviors are satisfactory with good interfacial quality. It can be concluded that the Kirkendall effect was prohibited by the previous Al2O3 film, and the second Al2O3 film could grow successfully. Thus electrical properties were demonstrated to be good. Under high electric field, F-N tunneling dominates the charge behaviors, while P-F mechanism rules the low electric field leakage current. Second, a treatment of 380℃ annealing in N2 ambient for the initial SiO2 effectively remove hydrogen or some unwanted ions. The C-V and J-V curves comparison between the samples with and without post SiO2 anneal had demonstrated the necessity of the interfacial SiO2 refinement. The leakage current can be suppressed more about 2 to 3 orders with SiO2 anneal. The constant current stress method was used to examine the reliability. From the voltage fluctuation during constant current stress, electron trapping behavior reveals that the post SiO¬2 anneal could also reduce the interface traps.

並列關鍵字

High-k gate dielectric ； Low temperature process ； Nitric acid oxidation

參考文獻

[1] Donald A. Neamen, “Semiconductor Physics and Devices: Basic Principles,” 3rd edition, published by McGraw-Hill, 2003.

[3] International Technology Roadmap for Semiconductor. [Online]. Available: http://www.itrs.net.

[6] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-kappa gate dielectrics: Current status and materials properties considerations” J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, 2001.

[8] K. J. Yang and C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46, pp. 1500-1501, July, 1999.

[9] Hang-Ting Lue, Chih-Yi Liu, and Tseung-Yuen Tseng, “An Improved Two-Frequency Method of Capacitance Measurement for SrTiO3 as High-k Gate Dielectric,” IEEE Electron Device Lett., vol.23, pp. 553-555, march, 2002.

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以遮蔽式蒸鍍及硝酸氧化技術低溫製備高介電係數氧化鋁閘極介電層

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