適用於高速串列傳輸之里德所羅門編解碼器設計及硬體實現

Design and Hardware Implementation of Reed-Solomon Codec for High-Speed Serial Transmission

黃仲瑋(Chung-Wei Huang)

指導教授 ： 曹恆偉

共同指導教授 ： 吳靜雄

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.10986

摘要

在高速數據串列傳輸的應用上，為了能夠偵測並且加以修正因為傳輸通道非理想特性而造成的錯誤，在傳輸時常常會將原來欲傳輸的訊號，編碼成帶有特殊樣式的錯誤更正碼，對抗來自於通道中的隨機錯誤或是叢集錯誤所帶來的影響。爾後透過解碼，偵測其接收的訊號中錯誤位置的所在，並且加以修正，以得到原來乾淨的訊息。里德所羅門碼，便是其中一種能夠偵測，並且加以更正的錯誤更正碼。

在晶片實作中，為了同時兼顧高速傳輸的需求，以及符合晶片中心對於下線面積的限制，我們實現了規格為(n,k,t)=(15,9,3)的里德所羅門編解碼器，在傳輸的15個符號單位中，其中有9個符號是原始訊息，且可更正至多3個符號的傳輸錯誤。在實作上使用TSMC 0.35μm 2P4M CMOS製程，電源供應為3.3 V，電路的速率可以達到125 MHz，晶片總面積為1.462 X 1.462 mm2，總功率消耗為197.3 mW。晶片量測採用國家晶片系統設計中心的混合訊號自動測試機台，驗證本晶片功能的正確性，並且將此里德所羅門編解碼器用於高速串列傳輸系統。

在高速串列傳輸之里德所羅門編解碼器系統實作中，使用Xilinx公司的ML507 Evaluation Platform做為開發平台，並且制定同步高速串列傳輸系統通信協議。定義一個框架為120位元，其中有4個同步位元，84個資料位元，以及32個錯誤更正碼冗餘位元。實現此通信協議使用以下模組，包含擾碼器和解擾碼器、里德所羅門編碼器和解碼器、交錯器和解交錯器、跨時脈域雙埠記憶體、同步位元對齊模組、串列器和解串列器。系統測試則使用迴路測試以及光纖通訊系統測試來驗證系統的正確性，成功實作一個可調整線速率範圍在3Gbps到5Gbps的高速串列傳輸之里德所羅門編解碼器系統。

關鍵字

錯誤更正碼 ； 通道編碼 ； 里德所羅門編解碼器 ； 高速串列傳輸系統 ； 同步串列通訊協議 ； 現場可程式化邏輯陣列 ； 數據通訊

並列摘要

In the application of the high-speed serial transmission, due to non-ideal transmission channel we usually encode original messages into the particular patterns, or so-called error-correcting code such that the errors can be detected and corrected. The channel noise may result from random noise and burst noise. Through decoding, these transmission errors can be detected and corrected. Reed Solomon code is one of the error-correcting code which is capable of detecting and correcting errors.

For chip implementation, considering the high-speed application and the limitations of chip area, we eventually implement a Reed-Solomon Codec whose specification is (n,k,t)=(15,9,3). In the other words, there are nine symbols of original messages over fifteen symbols during transmission and up to three error symbols can be tolerated. For the implementation, we use TSMC 0.35μm 2P4M CMOS process, and the voltage supply is 3.3 Volts. As the result, operating frequency of the circuit can be as high as 125 MHz, while the corresponding area is 1.462 X 1.462 mm2 and the total power consumption is 197.3 mW. In the chip measurements, we use the National Chip Implementation Center mixed-signal automatic test machine to verify the functionality of the chip. We could apply this Reed-Solomon Codec for the high-speed serial transmission systems.

In the implementation of Reed-Solomon Codec for high-speed serial transmission using the Xilinx ML507 Evaluation Platform as a development platform, we develop high-speed synchronous serial transmission system protocol that defines a frame of 120 bits, of which there are 4 synchronization bits, 84 data bits, and 32 redundant error-correcting bits. This protocol is implemented by using various modules, including scrambler and descrambler, Reed-Solomon Codec, interleaver and de-Interleaver, clock-domain-crossing dual-port RAM, synchronous bit alignment module, serializer and deserializer. In the system tests, we use the loop test and the fiber optic communications system test to verify the correctness of the system. We successfully implement a Reed-Solomon Codec for high-speed serial transmission system whose line rate range is 3Gbps to 5Gbps.

並列關鍵字

Error-correcting code ； Channel coding ； High-speed serial transmission system ； Reed-Solomon codec ； Synchronous serial communication protocol ； Field programmable gate arrays (FPGA) ； Data communications

參考文獻

[10] 高速串列通訊技術的發展、設計及應用

[22] 國家晶片系統設計中心, “混合訊號測試實驗室機台操作參考手冊”, 2009.

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[3] S. B. Wicker and V. K. Bhargava, Reed-Solomon Codes and Their Applications, IEEE Press, 1994.