基於現場可程式化邏輯閘陣列之支援符號伸展與反轉能力的高解析度格式器

A High-Resolution FPGA Formatter with Symbol-Stretching and Inversion Capability

蕭智隆(Chih-Lung Hsiao)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603765

摘要

格式器在自動測試機台中扮演重要的角色。其負責將測試向量、訊號格式及邊緣時序等資訊組合成測試訊號。ASIC格式器在市場上較為普遍，和FPGA格式器相比有較高的效能。因此，ASIC成為格式器的主流。然而，FPGA以其相對較低的開發成本、高設計靈活度以及不需要下線的優點，而有研究及發展的可能。
本論文提出的格式器實現在Xilinx Spartan-6 FPGA，支援多個區間的符號伸展與符號反轉功能。用硬體實現動態的(On-the-fly)符號伸展，讓格式器能在固定的系統時鐘(System clock)頻率的情形下，產生100、50、33.3、25 Msps的測試符號頻率的測試訊號。實驗結果顯示，提出的格式器能實現200 ps解析度的邊緣置放，其精確度為91 ps。

關鍵字

測試機台 ； 格式器 ； 現場可程式化邏輯閘陣列 ； 符號伸展 ； 可程式化延遲線

並列摘要

The formatter plays an important role in automatic test equipment. It is responsible for formatting the test signal with test vectors, signal formats, edge timings and other input data. ASIC designed formatters are more common in the market comparing to ones with FPGA designed, since ASIC formatters achieve higher performance generally. For this reason, ASIC design is the mainstream for formatter. However, FPGA format-ters still have potential, because FPGA design has the advantages of lower development cost, higher flexibility, and no need to tape-out.
In this work, the proposed formatter is implemented on Xilinx Spartan-6 FPGA, and it is supported with multiple interval symbol-stretching and symbol inversion func-tions. On-the-fly symbol-stretching is achieve with hardware, and it empowers the for-matter to generate test signals with 100, 50, 33.3, 25 Msps symbol rate without changing the frequency of system clock. The measurement results show that the proposed for-matter achieves 200 ps edge placement resolution and the accuracy is 91 ps.

並列關鍵字

test equipment ； formatter ； FPGA ； symbol-stretching ； programmable delay line

參考文獻

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