基於現場可程式化邏輯閘陣列實現可重構指令集架構 之軟硬體整合

Software and Hardware Integration for Reconfigurable Instruction Set Architecture based on FPGA

蘇莙傑(CHUN-CHIEH SU)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202201834

摘要

隨著資訊科技的快速發展，大家開始注重資訊安全的問題。單純使用傳統的軟體加密技術或是硬體加密技術越來越難保證資訊安全的可靠性，尤其是現在逆向工程的技術越來越發達，很多可執行檔的 binary code 可以很輕易透過反組譯工具逆向反組譯回組合語言甚至高階語言導致一些敏感機密資料外洩。在此背景下，本論文實現了一種針對 CPU 指令集架構進行軟體與硬體整合的雙向亂序加密框架。內容包括 MIPS ISA 和 CPU0 ISA 以及其對應的高階語言 Compiler tool chain的框架設計，利用 Quartus II 17.1 做 comprehensive wiring 以及利用 Modelsim 模擬驗證，最後燒錄到 FPGA(Altera DE2­115) 上，實驗結果顯示使用我們提出的框架生成出的 CPU 以及 compiler tool chain 可以正確無誤的執行並且只有微乎其微的overhead。

關鍵字

中央處理器 ； 指令集架構 ； FPGA ； LLVM ； 編譯器 ； 組合語言

並列摘要

With the rapid development of information technology, everyone has begun to pay attention to the issue of information security. It is becoming more and more difficult to ensure the reliability of information security by simply using traditional software encryption technology or hardware encryption technology, especially now that the technology of reverse engineering is more and more developed, and the binary code of many executable files can be easily decompiled through reverse translation. The tool reverses and decompiles back to the combined language and even the high­level language, which leads to the leakage of some sensitive and confidential information. Under this background, this paper implements a bidirectional out­of­order encryption framework that integrates software and hardware for CPU instruction set architecture. The content includes the framework design of MIPS ISA and CPU0 ISA and their corresponding high­level language Compiler tool chain, using Quartus II 17.1 for comprehensive wiring and M delsim simulation verification, and finally burning to FPGA (Altera DE2­115), the experimental results show that using The CPU and compiler tool chain generated by our proposed framework can be executed correctly and with only minimal overhead.

並列關鍵字

CPU ； ISA ； FPGA ； LLVM ； compiler ； assembly language

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