動態隨機存取記憶體之電容特性分析及自旋轉移力矩式磁阻式隨機存取記憶體模型模擬

The Characteristic Analysis of DRAM MIM Capacitor and STT-MRAM LLG-based Model

董宜承(I-Cheng Tung)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201901851

摘要

自從三星在2015年量產20nm DRAM產品後，DRAM的發展進入1X,1Y,1Z的時代，為了滿足微縮後的需求，如何在有限的面積裡維持足夠大的電容值防止讀取錯誤為DRAM微縮之主要問題，改變電容有效接觸面積或介電常數為主要解決方法，可用改變電容結構或改變材料來解決，然而高介電常數之材料勢必有較高漏電流，必須在滿足低漏電流情況下，尋求最高電容值之電容。另一方面近來，Spin-Transfer Torque Magnetic Radom Access Memory (STT-MRAM)已經成為下世代重要的非揮發性記憶體的，STT-MRAM是利用電流經Magnetic Tunneling Junction (MTJ)後形成自旋極化電流，能翻轉鐵磁薄膜中的電子磁矩造成電阻值改變作為存取資料的訊號，STT-MRAM有許多優點：非揮發特性、讀寫速度快、低能耗、高讀寫次數上限。
本論文第一部分研究以二氧化鋯為主之介電層作為DRAM電容，在原子層沉積過程中，在二氧化鋯介電層中成長一層氧化鋁形成二氧化鋯/氧化鋁/二氧化鋯薄膜，探討成長氧化鋁於二氧化鋯之位置對其介電層之電特性之影響，另外探討原子層沉積溫度變化對電特性之影響與氧化層可靠度分析，預測氧化層在DRAM正常操作下，電容壽命是否可達十年。另一部分，使用TCAD模擬分析氧化鋁在二氧化鋯中不同位置對漏電流之影響，並解釋不同位置的氧化鋁對非對稱電流之關係。
本論文第二部分以Landau-Lifshitz-Gilbert(LLG)公式為基礎，模擬電流流經垂直式MTJ(pMTJ)時，垂直式MTJ之磁矩隨時間變化導致高電阻阻態(HRS)與低電電阻阻態(LRS)的變化，此模型的準確性已與理論值進行驗證。另一方面利用其他文獻實驗參數進行模擬，依據Fokker-Planck理論，因熱擾動造成磁矩之初始角產生機率分布，使用Monte Carlo方法分析STT-MRAM之Write Error Rate(WER)可靠度分析，探討其參數對其影響並畫出Shmoo Plot分析在特定電流和時間內能夠達到WER標準值1E-6，並考慮製程所致垂直式MTJ之直徑與厚度誤差對可靠度之影響。

關鍵字

DRAM電容 ； 二氧化鋯-氧化鋁-二氧化鋯薄膜 ； TCAD模擬 ； STT-MRAM模擬 ； 可靠度分析

並列摘要

Since Samsung released 20nm DRAM products in 2015, DRAM has now migrated to the 1x, 1y, 1z era. The main challenge is how to maintain the sufficient capacitance in the limited area to prevent the sensing error as DRAM capacitor scaling. How to increasing the effective area of capacitor or decrease the equivalent oxide thickness (EOT) is the main solution. The problem could be solved by means of changing the structure or materials. However, high dielectric constant oxide generally has the lower energy gap. Therefore, under the condition of the low leakage current, achieve the minimum of equivalent oxide thickness (EOT) to be the next generation DRAM products. On the other hand, Spin-Transfer Torque Magnetic Radom Access Memory (STT-MRAM) has emerged as a promising candidate for the next generation of non-volatile memory. STT-MRAM switching the magnetization through Magnetic Tunneling Junction (MTJ) with polarized current to change their resistance state as data. STT-MRAM has many advantages, including non-volatility, high speed, low power dissipation, and high endurance.
In the first part, investigate on ZrO2-based film as DRAM capacitor. During atomic layer deposition (ALD) process, fabricate ZrO2-Al2O3-ZrO2 (ZAZ) film and investigate on the relationship between the locations of interposed layer Al2O3 and electrical characteristics. On the other hand, analyze the ZAZ film with the various location at the different ALD process temperature, and conduct time dependent dielectric breakdown (TDDB) analysis to prevent whether the dielectric has 10-year lifetime on the normal operation or not. In the next chapter, simulate the leakage current of ZAZ film with the various location of Al2O3 the by TCAD simulation, and explain the asymmetry factor of leakage current with the various location of Al2O3
In the second part, establish the model of perpendicular Magnetic Tunneling Junction (pMTJ) on the basis of Landau-Lifshitz-Gilbert (LLG) equation. Through the drive current, the dynamic magnetization as a function of time would be switched between high resistant state (HRS) and low resistant state (LRS). The accuracy of the model had been verified with the theorems. Furthermore, according to Fokker-Planck theorem, simulate the initial angle distribution of magnetization owing to thermal fluctuation. Based on the other’s experiment, run the LLG-based model many times to predict write error rate (WER) of STT-MRAM by means of Monte Carlo method and plot Shmoo plot to determine the operation point for WER=1E-6. On the other hand, analyze the change of reliability issue plot after considering the diameter and thickness variation of MTJ owing to process variation.

並列關鍵字

DRAM capacitor ； ZrO2-Al2O3-ZrO2 film ； TCAD simulation ； STT-MRAM simulation ； Reliability analysis

參考文獻

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