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  • 學位論文

高電壓4H-SiC接面位障蕭基二極體設計與製作

The Design and Fabrication of High Voltage 4H-SiC Junction Barrier Schottky Diode

指導教授 : 李坤彥

摘要


本論文使用碳化矽基板4H-SiC製作高電壓接面位障蕭基二極體元件(Junction barrier Schottky diode, JBS)。JBS元件在順向導通時有蕭基二體(SBD)低導通電壓、高切換速度的優點;逆向偏壓操作時能利用PN接面形成的空乏區夾住通道,因此有如PN二極體低漏電、高崩潰電壓的優點。 為了使元件有最好的順逆向IV特性表現,本論文設計了多種不同的P+離子佈植圖形:同心圓、片段式同心圓、長條形、方形陣列等及不同P+佈植間距,而產生不同面積比例的蕭基接面,並比較不同設計對其順向導通電壓、電流密度、逆向元件漏電流、崩潰電壓的影響。 依據量測結果,片段式同心圓與同心方形P+佈植圖形有較高的蕭基接面面積比例,因此有較好的順向IV特性表現,在高溫順向操作時也有較小的順向導通電壓偏移量;當元件P+佈植間距小於8um,逆向偏壓操作時PN接面形成的空乏區能將通道夾住,會有較好的漏電流與崩潰電壓表現。 本論文也進一步量測接面電容特性,利用SBD接面電容量測可進一步推測磊晶層N-的實際濃度、元件的內建電壓Vbi並計算實際蕭基位障值

並列摘要


In this research, C-face 4H-SiC substrates were used to fabricate junction barrier Schottky diodes (JBS), which have the forward characteristics of a low voltage drop and fast switching similar to a Schottky barrier diode (SBD). When a JBS is operated in reverse bias mode, it shows the characteristics of low leakage current and high breakdown voltage similar to a P-intrinsic-N diode (PiN). We have designed different kinds of P+ implant patterns such as concentric circles, segmented concentric circle, strips and square arrays with different distance between adjacent P+ implant regions. The different shape designs produce various ratios of Schottky contact area to PN junction areas. Then we analyzed the influence of the ratios on forward voltage drop, forward current density, reverse current density and breakdown voltage in different pattern designs. The segmented concentric circle and square arrays JBS show the better performance in forward operation, because of the higher Schottky contact area percentage. However, the square arrays JBS has higher leakage current. When the space between adjacent P+ implant regions is below 8um, JBS shows the characteristics of lower leakage current and higher breakdown voltage in reverse bias mode. We also measured the characteristics of junction capacitance of SBD to calculate the concentration of N- epi layer, built in potential Vbi and Schottky barrier.

並列關鍵字

4H-SiC JBS SBD P+ implant patterns Schottky barrier

參考文獻


[1] T. Kimoto, "SiC technologies for future energy electronics," in VLSI Technology (VLSIT), pp. 9-14, 2010.
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