4H型U型溝槽式閘極金氧半場效電晶體特性之研究

A Study on the Characteristics of 4H-SiC UMOSFETs

游嘉榕(Chia-Jung Yu)

指導教授 ： 崔秉鉞

國立交通大學/電機學院/電子工程系所/碩士(2018年)

摘要

寬能隙半導體功率元件可操作在高電壓、大電流的高溫環境，已經逐漸取代矽基功率元件。在諸多寬能隙半導體材料中，4H型碳化矽因為擁有高崩潰電場、好的熱傳導性而脫穎而出，但是在4H型碳化矽金氧半場效電晶體中，由於高的介面能態密度導致通導載子遷移率降低，而電荷幫浦 (Charge-pumping)方法可以直接量測到4H型碳化矽金氧半場效體晶體裡的介面能態密度。此外，而增厚底部氧化層 (TBOX)可以有效地降低U型溝槽式閘極金氧半場效電晶體底部氧化層的電場，在先前的研究中，P型井/N型磊晶接面漏電流是在製作傳統式U型溝槽式閘極金氧半場效電晶體 (C-UMOSFET)中主要的問題，我們必須先解決這個問題，而我們的最終目標是製作電性正常的厚底部氧化層U型溝槽式閘極金氧半場效電晶體 (TBOX-UMOSFET)。
　　我們使用電荷幫浦量測4H型平面式金氧半場效電晶體的介面能態密度，我們發現當脈衝的下降時間增加至3微秒時，幾何成分就會顯著地減少，這代表從介面能態中釋放的電子有足夠時間到達源極與汲極。此外，我們還量測了不同通導長度的4H型碳化矽平面式金氧半場效電晶體，並且發現幾何成分會造成介面能態密度的高估，最後我們將電荷幫浦法所萃取的介面能態密度來跟高低頻電容法 (High-low CV method)作個比較，電荷幫浦法所萃取的介面能態密度比高低頻電容法的高，這有可能是因為高低頻電容法的頻率不夠高導致低估介面能態密度。
　　我們發現用稀釋一氧化二氮成長氧化層的金氧半電容有很嚴重的移動離子效應 (Mobile ion effect)，我們利用電感耦合電漿體質譜法 (ICP-MS)及二次離子質譜儀 (SIMS)發現在氧化層裡有大量的鉀和納元素，他們可能是來自於氧化鋁晶舟，我們用平帶電壓漂移的量來計算出移動離子的濃度大約為3x1012 cm-2，這個濃度是用ICP-MS偵測到的百分之零點零七，這也可以說明為什麼我們在室溫下就可以觀察到遲滯效應。然而，在同樣的氧化製程下，平面式金氧半場效電晶體的Id-Vg特性卻沒有移動離子效應，這兩種金氧半結構最主要的差異在於閘極電極的不同，金氧半電容的閘極電極為鋁，而平面式金氧半場效電晶體的閘極電極則是多晶矽，後者可以用於集聚納與鉀離子，因此在室溫下才沒有明顯的遲滯效應，平面式金氧半場效電晶體的場效通道遷移率約為50~60 cm2/V-sec，次臨界擺幅為360 mV/decade，這個高通道遷移率可能不只是因為一氧化二氮鈍化的效果還有可能是因為鉀跟納摻雜的結果。
　　我們利用改良式平台結構隔絕P型井使接面漏電流密度降低4個數量級，並且成功地做出有正常開關特性的傳統式U型溝槽式閘極金氧半場效電晶體，用稀釋一氧化二氮成長氧化層的傳統式U型溝槽式閘極金氧半場效電晶體在閘極電壓為30V的通道遷移率大約為1.5~2.5 cm2/V-sec，次臨界擺幅則是1380 mV/decade。儘管氧化條件相同，傳統式U型溝槽式閘極金氧半場效電晶體卻有比平面式金氧半場效電晶體還差的次臨界擺幅以及較低的通導遷移率，這有可能是因為低品質的溝槽側壁導致較高的介面能態密度。為了了解通導遷移率劣化的機制，我們量測平面式以及U型溝槽式閘極金氧半場效電晶體的溫度效應，兩種電晶體的閘極氧化層都是在氬氣稀釋的一氧化二氮環境下進行氧化，對於平面式結構來說，次臨界擺幅以及通導遷移率的溫度相關性並不明顯，而傳統式U型溝槽式閘極結構的次臨界擺幅隨著溫度升高而變好，通導遷移率則是隨著溫度升高而變高，這些結果指出在氧化層與4H型碳化矽間有很高的介面能態密度，它們可能來自於蝕刻後的側壁損傷或是粗糙的側壁。
　　我們利用氬氣離子植入來局部性增加氧化速率以製作厚底部氧化層的結構，並且利用穿透式電子顯微鏡 (TEM)來檢視厚底部氧化層結構並做全面性的討論，底部氧化層厚度可以達到132奈米，是傳統結構的3.3倍。此外，厚底部氧化層U型溝槽式閘極金氧半場效電晶體的崩潰電壓比傳統的大10 V，而閘極-汲極電容則是比傳統式低141 fF，雖然本篇論文製作的厚底部氧化層U型溝槽式閘極金氧半場效電晶體仍然沒有導通特性，但是這些部分的測試結果肯定了厚底部氧化層結構的潛力。

關鍵字

碳化矽 ； U型漕槽式閘極金氧半場效電晶體 ； 金氧半場效電晶體

並列摘要

Wide bandgap semiconductors are promising materials to replace Si to implement high-voltage and high current power device operating at high temperature. Among those materials, 4H-SiC is the most promising candidate due to its physical property, such as high critical electric field and high thermal conductivity. However, the low mobility characteristics of 4H-SiC MOSFET results from high interface state density at the SiO2/4H-SiC interface. The charge-pumping method is a reliable technique to directly characterize interface state density in 4H-SiC MOSFET. Additionally, TBOX-structure is suitable to lower the electric field in the bottom oxide of UMOSFET. In our previous work, P-well/N-epi junction leakage current is a fabrication issue in conventional UMOSFET (C-UMOSFET), and it must be solved. Our ultimate goal is to demonstrate the advantages of TBOX-UMOSFET with normal on/off characteristics.
In this thesis, we use charge-pumping measurement to characterize the interface state density in 4H-SiC planar MOSFET. As the pulse fall time increases to 3 μsec, the current tail resulting from geometric component is strongly reduced, indicating that the electrons emitted from interface state have enough time to flow to source and drain. Besides, 4H-SiC planar MOSFETs with different channel lengths are characterized by charge-pumping method. The results show that the geometric component leads to overestimation in Dit. Finally, we make a comparison between charge-pumping method and high-low CV method. The Dit extracted from charge-pumping method is slightly higher than that extracted from high-low CV method, which is possibly due to the underestimation in high-low CV method. The underestimation is attributed to not high enough frequency in high frequency CV measurement.
We find that MOS capacitor, the gate oxide of which was grown in diluted N2O ambient, has severe mobile ion effect even though at room temperature, and the ICP-MS and SIMS analyses confirm the existence of potassium and sodium in the gate oxide. They are possibly originated from alumina boat. The concentration of the mobile ion is calculated as 3x1012 cm-2 by ΔVfb, which is 0.07% of that detected by ICP-MS. This is the reason why we can observe hysteresis effect at room temperature. However, the Id-Vg characteristics of the planar MOSFET under the same oxidation condition show no hysteresis effect at room temperature. The main difference of these two MOS devices is the gate electrode. The gate electrode of the MOS capacitor is aluminum while that of the planar MOSFET is in-situ doped polysilicon. The latter can getter sodium and potassium ions so that no apparent hysteresis is observed at room temperature. The field-effect mobility is about 50~60 cm2/V-sec, and subthreshold swing is 360 mV/decade. The high mobility might be not only a result of N2O passivation but also that of potassium and sodium incorporation.
For the P-well/N-epi junction leakage current issue, an improved mesa structure is used to isolate P-well. The junction leakage current density is reduced by 4 orders, and a C-UMOSFET with normal on/off characteristics is successfully fabricated. For the C-UMOSFET, the gate oxide of which was grown in diluted N2O ambient, the field-effect mobility of is about 1.5~2.5 cm2/V-sec at the gate voltage of 30 V, and the subthreshold swing is 1380 mV/decade. The C-UMOSFET has worse subthreshold swing and lower mobility than planar MOSFET, under that same gate oxidation condition. It might be due to the poor quality in trench sidewall, resulting in higher interface state in the C-UMOSFET. In order to realize the mechanism of mobility degradation, the high temperature measurements are performed on the planar MOSFET and C-UMOSFET, both of which have gate oxides grown in Ar-diluted N2O ambient. The temperature dependence on subthreshold swing and mobility is weak for planar MOSFET. As for C-UMOSFET, the subthreshold swing becomes steeper and mobility becomes higher as the temperature increases, indicating higher interface state at the SiO2/4H-SiC interface, which may result from etching damage and surface roughness.
For the TBOX-UMOSFET fabrication, we use Ar ion-implantation to locally enhance oxidation rate to fabricate TBOX structure. With the help of TEM, the TBOX structure is comprehensively discussed and inspected. The gate oxide thickness of the TBOX-UMOSFET at trench bottom is estimated to be 132 nm, which is 3.3 times thicker than that of the C-UMOSFET. Additionally, the breakdown voltage of the TBOX-UMOSFET is higher than that of the C-UMOSFET by 10 V, and the Cgd of the TBOX-UMOSFET is lower than that of the C-UMOSFET by 141 fF. Despite the fact that it still has no conduction characteristic, these results confirm potentials of the TBOX structure.

並列關鍵字

4H-SiC ； UMOSFET ； MOSFET

參考文獻

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