微波及毫米波系統關鍵元件之設計與研究

Design and Research of Key Components for Microwave and Millimeter-Wave Systems

黃梓原(Tzu-Yuan Huang)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2015年)

https://doi.org/10.6342/NTU.2015.02352

摘要

本論文中包含了三個部分，第一部分是一個切換式的相移器(switching type phase shifter)與可調增益放大器(variable gain amplifier)，並使用90-nm CMOS實現。因為在不同的相位狀態下，損耗將會改變，且引起振幅誤差。為了盡量減少STPS的振幅誤差。可調增益放大器將與相移器串聯，以補償在每個狀態下不同的損耗。此相移器與可調增益放大器在17.7-20.7 GHz頻段中展示了小於11.25度的相位誤差且可變增益放大器具有足夠的增益控制範圍，以彌補STPS所造成的振幅誤差。
第二部分提出一新架構之分佈式放大器並由0.18-μm CMOS實現。此架構為分佈式放大器使用漸進式放大電晶體(DA with taper-sized transistors)和串接單級分佈式放大器(CSSDA)的組合。此分佈式放大器可以同時考慮增益頻寬積(GBW product)，輸出功率，雜訊指數(NF)與直流功耗。透過分佈式放大器使用漸進式放大電晶體，可以有效降低直流功率，同時維持射頻功能。此分佈式放大器可以達到25-dB小訊號增益和34 GHz的3-dB頻寬，且僅需176 mW直流功耗。最大輸出功率1dB壓縮點為7.2 dBm，而雜訊指數在5 GHz到25 GHz間介於6.5 dB到8 dB。此電路在已發表的0.18 μm CMOS分佈式放大器中，展現了最高的效能指數(FOM)，且與以其他高階製程所設計之分佈式放大器相比也有相稱的特性。
第三部分為一功率放大器（PA）由0.18-μm CMOS實現，同時採用適應偏壓電路和預失真線性化電路。此功率放大器使用適應偏壓技術，提昇較小輸入功率時的功率附加效率，且預失真線性化電路可以改善輸出功率1 dB壓縮點，進而提升此功率放大器的線性操作範圍。此電路在輸出功率1 dB壓縮點後退6 dB操作顯示了6.8％的功率附加效率，在輸出功率1dB壓縮點得到14.1％的功率附加效率，同時在輸出一階項訊號必須比三階項雜訊高40dBc的條件下線性輸出功率為9.2 dBm。

關鍵字

互補式金屬氧化物半導體 ； 切換式相移器 ； 可調增益放大器 ； 分佈式放大器 ； 功率放大器

並列摘要

This thesis consists of three parts. The first part is a switching type phase shifter (STPS) and variable gain amplifier (VGA) using 90 nm CMOS technology. Different insertion losses while changing phase states will cause the amplitude error. To minimize the amplitude error of the STPS, a variable gain amplifier can be cascaded with the phase shifter to compensate the different loss at each state. The measured phase error is under 11.25° in 17.7 to 20.7 GHz. The variable gain amplifier has enough gain control range to cover the amplitude error caused by STPS.
The second part is a distributed amplifier (DA) using new topology developed in 0.18-μm CMOS. The topology uses the combination of the DA with taper-sized transistors and the cascaded single-stage distributed amplifier (CSSDA). This proposed DA takes considerations of gain-band width (GBW) product, output power, noise figure (NF), dc power consumption, and compact size. By using DA with taper-sized transistors, this DA reduces dc power consumption while maintaining the RF performance. This DA achieves 25-dB gain and 34 GHz 3-dB bandwidth with total dc power of 176 mW. The maximum OP1dB is 7.2 dBm and the NF is between 6.5 and 8 dB at frequency lower than 25 GHz with the compact size of 0.86 mm2. This circuit exhibits the best figure of merit (FOM) in 0.18-μm CMOS and comparable performance with the DAs in advanced process.
The third part is a power amplifier (PA) developed in 0.18-μm CMOS. The topology adopts the adaptive bias and pre-distortion linearizer simultaneously. The design of this PA takes back-off efficiency, linear output power, and quiescent power consumption into consideration. After linearization, the proposed PA achieves 6.8% PAE at 6-dB back-off from P1dB, 14.1% PAE at OP1dB, and high linear output power 9.2 dBm with third-order intermodulation distortion (IMD3) of -40 dBc. This circuit shows good performance compared with the published PAs in 0.18-μm CMOS and suitable for high data rate transmission applications.

並列關鍵字

CMOS ； switching type phase shifter ； variable gain amplifier ； distributed amplifier ； power amplifier

參考文獻

[1] Matthew A. Morton, Jonathan P. Comeau, John D. Cressler, Mark Mitchell, and John Papapolymerou, “Sources of phase error and design considerations for silicon-based monolithic high-pass/low-pass microwave phase shifters,” IEEE Trans. Microw. Theory Tech., vol. 54, no 12, pp. 4032-4040, Dec. 2006.

[2] Dong-Woo Kang, and Songcheol Hong, “A 4-bit CMOS phase shifter using distributed active switches,” IEEE Trans. Microw. Theory Tech., vol. 55, no 7, pp. 1476-1483, Jul. 2007.

[3] Masatake Hangai, Morishige Hieda, Norihiro Yunoue, Yoshinobu Sasaki, and Moriyasu Miyazaki, “S- and C-band ultra-compact phase shifters based on all-pass networks,” IEEE Trans. Microw. Theory Tech., vol. 58, no 1, pp. 41-47, Jan. 2010.

[4] Byung-Wook Min and Gabriel M. Rebeiz, “Ka-band BiCMOS 4-bit phase shifter with integrated LNA for phased array T/R modules,” in IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2007, pp. 479-482.

[6] Pei-Si Wu, Hong-Yeh Chang, Ming-Fong Lei, Bo-Jr Huang, Huei Wang, Cheng-Ming Yu, and John G. J. Chern, “A 40-74 GHz amplitude/phase control MMIC using 90-nm CMOS technology,” in European Microwave Integrated Circuits Conference., Oct. 2007, pp. 115-118.