應用於無線通訊之瓦級高功率密度變壓器功率結合式LDMOS功率放大器之研製

半導體製程的演進隨著無線通訊系統的發展，以互補式金氧半場效電晶體(CMOS)實現具成本優勢的射頻電路逐漸成為市場焦點，其中功率放大器是收發機中最關鍵的電路。本論文將著重於橫向擴散金屬氧化物半導體(LDMOS)技術研製，因著高崩潰電壓，分別設計了兩顆40奈米製程的功率放大器。第一顆電路是以達到功率放大器之高功率密度的優點，大幅減小晶片面積以節省成本。第二顆電路為瓦級之高輸出功率的功率放大器，隨著高傳播速率和遠距離的需求，達到3.5-GHz頻段使用CMOS的製程，以提高電路整合性和降低成本。在第三章，以40奈米互補式金氧半場效電晶體製程實現一個3.5-GHz LDMOS的變壓器功率結合式功率放大器。此運用頻段為4G/LTE手機通訊晶片，上傳頻寬為80MHz，是由3410MHz到3490MHz，中心頻率為3450MHz。LDMOS常被應用在設計給基地台使用的射頻功率放大器，原因是藉由較高的跨壓以滿足高輸出功率。為了降低晶片面積，功率放大器的功率核心使用變壓器以同時達成功率結合、阻抗匹配以及單端與差動訊號的轉換。在選擇較大的電晶體時，電晶體在柵極和漏極之間固有的電容也隨之增大，造成放大器不穩定的現象，插入一對中和電容不僅可以消除柵極和漏極之間的電容，以提高功率放大器的穩定性，同時也能達到提高增益的效果。此功率結合的功率放大器是目前此頻段附近的互補式金氧半場效電晶體最高的高功率密度，輸出功率可達到26.5dBm最大的輸出功率的設計，面積僅佔0.259平方毫米，可達到1724mW/mm2的飽和輸出功率的高功率密度，以及992.4mW/mm2的OP1dB輸出功率的高功率密度。在第四章中，以40奈米互補式金氧半場效電晶體製程實現一個具三維結構之 3.5-GHz瓦等級變壓器功率結合式功率放大器。為了達到近瓦等級的輸出功率，採用放射狀功率分配器及放射狀功率合成器將四路功率核心的功率結合輸出，因輸入端的分配器較不需考量損耗，走線同時具有阻抗轉換的功能以降低輸入端匹配網路的阻抗轉換比，而輸出端的合成器相對需要考量輸出功率，用最短距離的走線以降低損耗。藉由將放射狀功率分配器及合成器在電路的中央以三維結構垂直共用同一區域，突破以往二維功率結合技術的瓶頸，且可以在不用妥協和不受頻段限制的情況下同時達到電路佈局的對稱性和阻抗選擇的自由度，大幅減小功率分配器以及功率合成器的占用面積，達到縮小晶片面積的目的。此瓦級的三維架構功率結合的功率放大器是目前3.5-GHz頻段中，使用CMOS製程達到最高至瓦級的輸出功率，此輸出功率最高可達到31.26 dBm。

關鍵字

功率放大器；橫向擴散金屬氧化物半導體；變壓器結合；高輸出功率；高電壓操作；高功率密度； 40奈米互補式金氧半場效電晶體製程

並列摘要

With the evolution of semiconductor process and development of wireless communication system, implementing radio frequency integrated circuit with CMOS becomes the focus point of industry market. In the transceiver design, power amplifier is the most critical and significant component. This thesis emphasizes the design and analysis of laterally diffused metal oxide semiconductor (LDMOS). Due to the high supply voltage, two LDMOS power amplifiers in 40-nm process are designed and analyzed separately. The first power amplifier design achieves high power area density to reduce the chip area and cost effective. In order to target the demand of high data rate and long distance, the second power amplifier design obtains a watt-level high output power that becomes high output power performance in 3.5-GHz band that is in CMOS process to raise circuit integrity and reduce cost. In chapter 3, a compact 3.5-GHz transformer combined power amplifier with LDMOS transistors is designed in 40-nm CMOS process. This frequency band can be applied in 4G/LTE mobile devices, where has 80MHz bandwidth for uploading from 3410MHz to 3490MHz with the central frequency of 3450MHz. LDMOS is usually used in the design of RF power amplifiers in the base station since the high breakdown voltage provides high output power. In order to reduce the chip size, the power cells of power amplifier use transformer to do power combining, impedance matching and single-to-differential ended simultaneously. Larger device selection will bring larger gate-to-drain capacitance and it will make power amplifier instable. The neutralization capacitor can degrade the gate-to-drain capacitance, and effectively increase the stability and gain for power amplifier design. This power amplifier is the highest power density about the frequency bands in the recent power amplifiers of CMOS process. The output power can reach the highest performance as 26.5 dBm with only 0.259 mm2, and achieves in the highest power area density of saturated output power as 1724 mW/mm2 and the highest power area density of OP1dB as 992.4 mW/mm2. In chapter 4, a 3.5-GHz watt-level transformer combined power amplifier with 3-D architecture implements in 40-nm CMOS process. For watt-level output power design, 4-ways power combining is realized by the shortest path for the radial power combiner and longer path for the radial power splitter. The long path of input splitter can also reduce the impedance transform ratio of input matching network. By sharing the same area vertically in 3-D architecture, the occupied area of radial power combiner and power splitter can be minimized significantly. This technique breaks the bottle neck of the conventional 2-D power-combined techniques that achieves the symmetry of circuit layout and flexibility of impedance transformation without compromising and limiting in various conditions of different frequency bands. This watt-level 3-D architecture transformer-combined power amplifier achieves the highest output power in CMOS process among the recent published 3.5-GHz band power amplifiers. The maximum output power can be achieved in 31.26 dBm of high output power performance.

並列關鍵字

Power amplifier ； LDMOS ； Transformer combining ； High power ； High operating voltage ； High power area density ； 40-nm CMOS process

參考文獻

[58]蕭淯方撰，具三維結構之K頻段CMOS變壓器結合式功率放大器與效率改善技術之研究，國立台灣大學電信工程研究所碩士論文，2013年6月

[61]黃梓原撰，微波及毫米波系統關鍵元件之設計與研究，國立台灣大學電信工程所碩士論文，2015年1月

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應用於無線通訊之瓦級高功率密度變壓器功率結合式LDMOS功率放大器之研製

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