具三維結構之K頻段CMOS變壓器結合式功率放大器與效率改善技術之研究

Research of K-band CMOS Transformer Combined Power Amplifier With 3-D Architecture and Efficiency Enhancement Technique

蕭淯方(Yu-Feng Hsiao)

指導教授 ： 黃天偉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00916

摘要

隨著無線通訊的發展，以互補式金氧半場效電晶體製程實現之射頻積體電路逐漸受到市場重視，在收發機中以功率放大器為最關鍵的電路。因此本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。
在第二章中，以180奈米金氧半場效電晶體製程實現一個24-GHz超微小面積之功率放大器。為了微小晶片面積的設計，此功率放大器在輸出及輸入端採用變壓器同時實現功率結合、阻抗匹配及單端和差動訊號轉換的功能。透過推挽式的架構在電路對稱中心產生一虛擬接地，直流偏壓可被直接饋入而不需大容值的旁路電容，晶片面積可進一步的縮小。此功率放大器在24-GHz附近頻段達到最小的晶片面積0.26mm2及最高的面積使用效率。
在第三章中，以65奈米金氧半場效電晶體製程實現一個具三維結構之K頻段高輸出功率變壓器結合式功率放大器。為了達到高輸出功率，以放射狀功率分配器及放射狀功率結合器實現八路的功率結合，此放射狀網路也同時具有阻抗轉換的功能以減少輸入及輸出端匹配網路因高阻抗轉換比所造成的損耗。由於放射狀架構使得功率分配器及功率結合器能夠以三維的結構在電路中央共用同一區域的面積，因此功率分配器及功率結合器所需佔用的面積將可大幅縮小。此功率放大器在K頻段達到最大的飽和輸出功率26.1dBm並同時保有良好的面積使用效率。
在第四章中，以180奈米金氧半場效電晶體製程實現一個2-GHz的Doherty功率放大器。將含有λ/4架構的被動元件在晶片外以FR-4板材實現，使晶片面積縮小並降低元件造成的損耗以提升效率。此功率放大器呈現20% 的功率附加效率 (PAE) 並在6 dB功率回退時 (power back-off) 仍保有19%的功率附加效率。

關鍵字

功率放大器 ； 變壓器結合 ； 三維結構 ； 高輸出功率 ； 放射狀架構 ； Doherty

並列摘要

With the development of wireless communication, the radial frequency integrated circuit with CMOS technology is valued gradually in the industry. Among the transceiver, power amplifier is the most critical component. As the reasons, the design and analysis of CMOS power amplifier is focused in this thesis.
In chapter 2, an ultra-compact 24-GHz power amplifier implemented in 180-nm CMOS process. For compact chip size design, transformers are adopted to accomplish the functions of power combining, impedance matching and single-to-differential ended simultaneously. A virtual ground is generated at the symmetry of circuit by push-pull topology. DC bias can be fed directly without large value bypass capacitors, and the chip size is further reduced. The power amplifier achieves the smallest chip size 0.26 mm2 and the highest area efficiency around 24-GHz.
In chapter 3, a K-band high output power transformer combined power amplifier with 3-D architecture implemented in 65-nm CMOS process. In order to achieve high output power, 8-ways power combining is realized by the radial splitter and radial combiner. The radial networks with the function of impedance transformation to alleviate the loss of input and output matching networks caused by large impedance transformation ratio. Thanks to the radial structure, the power splitter and power combiner can share the center area of the circuit by a 3-D architecture, therefore the area occupied by power splitter and power combiner can be reduced significantly. The power amplifier achieves the highest saturated output power 26.1 dBm with excellent area efficiency at K-band.
In chapter 4, a 2-GHz Doherty power amplifier implemented in 180-nm CMOS process. All passive elements with λ/4 topology are fabricated off-chip on FR-4 board to diminish the chip size and mitigate the loss caused by elements to improve efficiency. The power amplifier performs 20% PAE and maintains 19% PAE at 6 dB power back-off.

並列關鍵字

Power amplifier ； Transformer combining ； 3-D architecture ； High power ； Radial structure ； Doherty

參考文獻

[7] 廖信強撰，適用於高速傳輸系統之毫米波高鏡像抑制調變器設計與D頻帶功率放大器之研製，國立台灣大學電信工程研究所碩士論文，2012年7月。

[35] 蔡政翰撰，毫米波發射器線性化及十億位元無線通信系統，國立台灣大學電信工程研究所博士論文，2007年1月。

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