三維積體電路關鍵技術與異質接合製程平台之電性與可靠度研究

Development, Electrical Performance, and Reliability Investigations of 3-D ICs Key Technologies and Hybrid Bonding Process Platform

張耀仁(Yao-Jen Chang)

指導教授 ： 陳冠能

國立交通大學/電機學院/電子工程系所/博士(2016年)

摘要

無資料

關鍵字

三維積體電路 ； 混和接合 ； 矽晶直通孔

並列摘要

無資料

並列關鍵字

3DIC ； Hybrid bonding ； TSV

參考文獻

[1] H.-S. Wong, “Beyond the conventional transistor,” IBM Journal of Research and Development, vol. 46, no. 2.3, pp. 133-168, 2002.

[2] V. Agarwal, M. Hrishikesh, S. W. Keckler, and D. Burger, Clock rate versus IPC: The end of the road for conventional microarchitectures: ACM, 2000.

[4] G. G. Shahidi, "SOI technology for the GHz era." pp. 11-14.

[5] M. Ieong, J. Kedzierski, Z. Ren, B. Doris, T. Kanarsky, and H.-S. Wong, “Ultra-thin silicon channel single-and double-gate MOSFETs,” SOLID STATE DEVICES AND MATERIALS, pp. 136-137, 2002.

[6] J.-T. Park, and J.-P. Colinge, “Multiple-gate SOI MOSFETs: device design guidelines,” Electron Devices, IEEE Transactions on, vol. 49, no. 12, pp. 2222-2229, 2002.