多執行緒微處理器設計

Multithreading CPU Design

陳育麟(Yu-Lin Chen)

指導教授 ： 陳中平

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.01854

摘要

效能是由總處理量來衡量的。總處理量越高，效能就越高。指令層級平行化﹙Instruction-Level Parallelism﹚與執行緒層級平行化﹙Thread-Level Parallelism﹚是兩個主要用來提升微處理器效能的技術。本論文是設計一個與ARM相容的微處理器，其指令層級平行化由6級的管線處理來實現，而執行緒層級平行化則由支援2個fine-grained的多執行緒來實現。為了功率消耗的效率，從架構的階層往下到邏輯閘的階層，有許多設計是與低功率設計有關的。

關鍵字

多執行緒 ； 平行化 ； 微處理機 ； 低功率

並列摘要

Performance is measured by throughput. The higher the throughput, the higher the performance. ILP (Instruction-Level Parallelism) and TLP (Thread-Level Parallelism) are two major technologies to improve CPU’s performance. This thesis is to design a 6-stage pipelined ARM-like CPU to fulfill ILP, and then develop it to TLP with a 2-thread fine-grained multithreading. For power efficiency, a lot of work has been done on low power design from architecture level down to gate level.

並列關鍵字

multithreading ； parallelism ； microprocessor ； low power

參考文獻

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