基材鰭式場效電晶體與鍺量子井場效電晶體之模擬研究

Simulation Study of Bulk FinFET and Ge Quantum Well pFET

張弘志(Hung-Chih Chang)

指導教授 ： 劉致為

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.01864

摘要

基材鰭式場效電晶體具有散熱佳，低製造成本，與傳統場效電晶體製程相容等優點。結合RCAT與三面閘極的結構展現非常優異壓制短通道的能力。在模擬結果顯示該結構具有良好的SS及DIBL的電性特徵。由於載子在完全空乏的鰭式通道流動，臨界電壓會受到鰭式通道的寬度及高度影響，必須重新修正。相較於RCAT 結構，基材鰭式場效電晶體對於凹槽深度及反向基板偏壓的變化較為不敏感。為了降低漏電流，在通道加上較高的參雜濃度，同時也會有較好控制能力。而汲極輕度參雜(LDD)被用來減低價帶至導帶的穿隧電流。同時，增加閘極-汲極氧化層厚度可以在犧牲少許控制能力的狀態下有效減低漏電流。
應用於未來高速元件的一種 Si-cap/Ge/Si 結構以模擬方式探討它的特性。Si-cap假設為完全張弛，而鍺通道層假設為完全應變。90-nm 平板矽場效電晶體一搬須要有HALO怖植以降低短通道效應。矽鍺異質結構造成的量子井可以將電洞侷限在鍺通道內。模擬結果顯示，相較於矽元件，此舉可以增加閘極的控制能力。Ge的BTBT性質在分析後放入計算中。不同的矽覆蓋層與鍺通道厚度所造成的漏流增減均進行模擬驗證

關鍵字

場效電晶體 ； 基材鰭式場效電晶體 ； 臨界電壓 ； 量子井

並列摘要

Bulk FinFET has advantages of heat dissipation, wafer cost, process compatibility and extendibility of conventional planar MOSFET technologies. The combination of recess channel array transistors (RCAT) technology and triple-gate in bulk silicon prove excellent SCEs control ability. It owns superior subthreshold slope (~70 mV/dec) and DIBL characteristics in simulation works. Due to the fully depleted fin channel, the subthrehold voltage is modified by not only channel doping but also the fin width and fin height. The saddle-like FinFET structure shows good immunity of electric characteristics of recess depth variation and reverse body bias comparing to RCAT structure. To integrate with DRAMs process, the leakage current must be suppressed. With higher channel doping, it reduces the Ioff current and subthreshold slope. By adopting LDD in S/D region, the band-to-band-tunneling generation is smaller. Also, increasing the thickness of gate-to-drain oxide, can help the leakage
suppression a lot but only a slightly control ability sacrifice.
A Si-cap/Ge/Si pFET structure based on 90-nm node for future high-speed transistor application is simulated. The Si-cap is assume to be relax and Ge layer is fully strained. For 90-nm node planar control-Si device, HALO implantation is necessary to reduce the SCEs. The Si-cap/Ge heterostructure results in the holes confinement in the quantum well, which provide better control ability comparing to control-Si device. The BTBT model for Ge is analyzed and put into simulation. The leakage due to smaller bandgap of Ge is examined by different Si-cap thickness and
Ge layer thickness.

並列關鍵字

MOSFET ； Bulk FinFET ； Threshold Voltage ； Quantum Well

參考文獻

Chapter 1

[1] G. E. Moore, "Cramming more components onto integrated circuits," Electronics,

[2] G. E. Moore, "No exponential is forever: but "Forever" can be delayed!," Proc.

[5] Kinam Kim, “Technology for sub-50nm DRAM and NAND Flash Manufacturing”, Technical Digest IEDM , p.323, 2005

[6] Q. Ouyang, X. Chen, S. P. Mudanai, X. Wang, D. L. Kencke, Al F. Tasch, L.