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  • 學位論文

鰭式場效電晶體刃差排應力源之應力與電性分析

Analysis of Stress and Electrical Characteristics of FinFETs with Edge Dislocation Stressors

指導教授 : 劉致為
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摘要


源極和汲極裡的刃差排(edge dislocation)應力源會對場效電晶體的通道裡產生拉伸應力,而本篇論文提出了其應力場之數學模型,利用此模型來分析場效電晶體內之應力場,並且優化差排應力源。該模型的精準度與有限元素方法所得到之模擬結果相似,透過其能夠深入瞭解差排應力源的物理性質,愈淺的差排會在通道邊緣的虛擬源極產生愈大的拉伸應力。對於某特定深度的差排來說,其核心與通道邊緣有一個適當的距離,能對虛擬源極產生最大的拉伸應力。 這樣的刃差排應力源也被用於鰭式場效電晶體(FinFET),同樣的,愈淺的差排會在鰭式場效電晶體之虛擬源極的頂端造成愈大的拉伸應力。為了產生更大的拉伸應力,本篇論文提出了一個新穎的應力源——多重刃差排應力源(multi-edge-dislocation stressor),並以模擬來驗證此應力源能有效提升拉伸應力。 為能精準模擬鰭式場效電晶體之電性,本篇論文深入探討其遷移率模型等物理機制,使其模擬結果與實驗數據相吻合。透過電性的分析,比較矩形和錐形之鰭式場效電晶體,發現矩形之鰭式場效電晶體有較大的飽和電流與較好的次閾值斜率(subthreshold slope)。除此之外,結果顯示差排核心愈深、距離通道邊緣愈近,愈能提升飽和電流。

並列摘要


Dislocation stressors in the source and drain build the tensile stress field in the channel of NMOSFET. An analytic model of the strain/stress field induced by the edge dislocation is presented. The model is used for stress optimization of the dislocation stressors in the NMOSFET channel. The accuracy of the model is similar to that of the finite element simulation. The closed-form solution provides a physical insight into the dislocation stressor. The analytic solution indicates that shallower dislocations generate a larger tensile stress at the edge of the channel near the virtual source. For a given dislocation depth, an optimal distance of the dislocation core from the edge is required to generate the maximum tensile stress at the channel edge. The edge dislocation stressors are also incorporated into FinFETs. A shallower dislocation induces larger stress field along the channel at top of the virtual source in the FinFET. A novel stressor, multi-edge-dislocation stressor, is proposed to induce larger stress field. Mechanisms for electrical simulations of FinFETs are carefully investigated and the accuracy of the simulation with fitted parameters is similar to the experimental data. Comparison between taper-shaped and rectangular FinFETs are studied that a rectangular FinFET has larger saturation current and better subthreshold slope than a taper-shaped FinFET does. Edge dislocations with shorter distance to the channel edge will enhancement the performance of FinFETs more. And the optimal depth of the edge dislocation is 34 nm, which is the same as the fin height.

參考文獻


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