三維積體電路之直通矽晶連通柱的傳輸特性萃取與損耗補償

隨著電子用品尺寸縮小，如何在有限空間中極大化積體電路的功能成為相當重要的議題。三維積體電路透過垂直堆疊結構將多功能晶片整合於較小的體積中，為目前最具可行性的方案。垂直堆疊結構裡最常使用的技術為鎊線與微凸塊，但由於直通矽晶連通柱具有較短傳輸路徑、較高輸入輸出密度與較低製造成本的優勢，因此逐漸受到重視。然而，萃取垂直堆疊多層直通矽晶連通柱的傳輸特性不僅代價高昂，實作可行性也低。此外，多層直通矽晶連通柱的損耗特性會造成訊號失真，降低訊號完整度。根據上述兩點，本篇論文提出兩組鍊狀型結構進行多層直通矽晶連通柱傳輸特性萃取，並設計一組電阻電容型等化器以改善訊號失真的問題。在傳輸特性萃取的部份，本篇論文提出兩組鍊狀型結構，透過將直通矽晶連通柱水平連結，達到模擬垂直堆疊的直通矽晶連通柱的目標。此外，亦針對兩組鍊狀型結構分別設計相對應的校準方式，以除去傳輸線效應與訊號直通矽晶連通柱間的耦合效應。研究成果將有助於以低成本且高可行性的方式萃取垂直堆疊的直通矽晶連通柱傳輸特性。在損耗補償的部份，本篇論文根據簡化的直通矽晶連通柱等效電路設計一組電阻電容型等化器，具有低功耗、高頻寬與適用於廣泛製程的優勢。此外，以十層垂直堆疊的直通矽晶連通柱結構為案例，分析本篇論文所提出的電阻電容型等化器效能，並檢視實際製作的可能性。透過採行此電阻電容型等化器，可大幅降低訊號失真的問題，提昇訊號傳輸品質與系統整體效能。

關鍵字

特性萃取；直通矽晶連通柱；耦合效應；等效傳輸矩陣

並列摘要

Optimizing the performance of integrated circuits (IC) in a limited space has become an important issue as electronic devices continue to decrease in size. One of the most promising technologies that aim to solve this issue is called three dimensional integrated circuits (3D-IC), which stacks ICs vertically. Compared to traditional techniques such as wire-bonding and microbumps, through-silicon-via (TSV) provides shorter transmission paths, higher input/output (I/O) density and lower cost. However, characterization of stacked TSVs is difficult and expensive. Furthermore, lossy TSVs may damage the signal integrity of systems. Therefore, this thesis proposes a solution consisting of two structures and an equalizer to solve the problems mentioned above. In order to extract the transmission effect of a single TSV, two sets of horizontally connected TSVs are designed. Under weak coupling conditions, the effect caused by transmission lines and coupling among signals can be eliminated through a calibration mechanism. Hence, extraction results can be used to predict the behavior of stacked TSVs. In addition, the characterization of TSVs is much more feasible and can reduce costs by using the methods. The design formulas of RC equalizers can be derived from the simplified equivalent circuit model of TSVs. Since mutual capacitance between TSVs has been taken into consideration, this RC equalizer can be applied to most processes operating in high frequencies. In addition, RC equalizers have lower power consumption and can provide wideband compensation. At the end, a structure of ten stacked TSVs is taken as an example to demonstrate the performance of RC equalizers and to evaluate the feasibility as well. The result shows that implementing RC equalizers can significantly improve the quality of signals.

並列關鍵字

characterization ； calibration ； coupling ； equivalent transmission matrix

參考文獻

[1] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: The pros and cons of going vertical,” IEEE Design Test Computers, vol. 22, no. 6, pp. 498–510, Nov. 2005.

[2] J. S. Pak, C. Ryu, and J. Kim, “Electrical characterization of through silicon via (TSV) depending on structural and material parameters Based on 3D full wave simulation,” in Int’l. Conf. Electron. Mat. Packag., Yuseong-gu, Daejeon, Korea, Nov. 11–19, 2007.

[3] N. Kim, D. Wu, D. Kim, A. Rahman, and P. Wu, “Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV),” in IEEE Electron. Compon. Technol. Conf., Lake Buena Vista, Florida, USA, May 31–June 3, 2011, pp.1160–1167.

[7] C.-H. Lin, C. Liu, H.-K. Huang, K.C. Fan, and H.-H. Lee, “Electrical model analysis of RF/high-speed performance for different designed TSV patterns by wideband double side measurement techniques,” in Int’l. Microsyst., Packag., Assemb. Circuits Technol. Conf., Taipei, Taiwan, ROC, Oct. 24–26, 2012, pp.72–75.

[8] K.-C. Lu, T.-S. Horng, H.-H. Li, K.-C. Fan, T.-Y. Huang, and C.-H. Lin, “Scalable modeling and wideband measurement techniques for a signal TSV surrounded by multiple ground TSVs for RF/high-speed applications,” in IEEE Electron. Compon. Technol. Conf., San Diego, California, USA, May 29–June 3, 2012, pp. 1023–1026.

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三維積體電路之直通矽晶連通柱的傳輸特性萃取與損耗補償

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