利用三維積體電路堆疊選擇使矽晶穿孔數目最小化之研究

TSV Number Minimization by Stacking Selection

曾韋碩(Wei-Shuo Tzeng)

指導教授 ： 黃世旭

中原大學/工學院/電子工程研究所/碩士(2012年)

https://doi.org/10.6840/cycu201200971

摘要

在矽晶穿孔架構下的三維積體電路，因為矽晶穿孔可能會影響電路的穩定度、面積、成本以及良率等等問題，所以如何有效減少矽晶穿孔的使用量，在三維積體電路設計上是非常重要的議題。在此篇文獻中，提出了使用堆疊方式選擇，提供至高階合成階段使用，藉此我們可以利用堆疊選擇方式的不同，如面對面、面對背以及背對背這三種堆疊方式選擇，將連線數量較多的鄰近層使用面對面的堆疊方式，次之的使用面對背的方式堆疊，最後鄰近層連線數量極少或者為零，才使用背對背的堆疊方式。我们提出以後處理的方法，使用整數線性規劃求得最佳的堆疊方式選擇。實驗主要分為兩個部分，分別為採用先前文獻的階層指派後結果以及採用先前文獻的資源連結後結果兩個後處理方法，實驗結果驗證此方法可以有效降低三維積體電路上的矽晶穿孔數量。

關鍵字

三維晶片 ； 堆疊選擇 ； 直通矽晶穿孔 ； 高階合成 ； 整數線性規劃

並列摘要

Minimizing TSV (Through-Silicon-Via) number is very important in 3D IC design, because TSV will increase the cost and the area, impact the circuit reliability, and reduce the die yield. There is a demand to reduce TSV number effectively in 3D IC design. In this thesis, we introduce the die stacking selection for TSV number minimization in high-level synthesis stage. There are three types of die stacking: face-to-face, face-to-back, back-to-back. We prefer the face-to-face stacking for the adjacent layers which have the most interconnects in order to minimize TSV number. We propose an integer linear programming (ILP) approach to solve this problem optimally. Experimental results consistently show that our approach can effectively reduce the TSV number in 3D IC Design.

並列關鍵字

Integer Linear Programming ； Stacking Selection ； High-Level Synthesis ； Through-Silicon-Vias ； Three-Dimensional Integrated Circuits (3D ICs)

參考文獻

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