利用替代路徑最小化三維晶片
直通矽晶穿孔數目之方法研究

減少直通矽晶穿孔數目在三維晶片設計中，是很重要的課題。在三維晶片，直通矽晶穿孔是用來進行在不同階層的資料傳輸。然而，直通矽晶穿孔對於佈局、繞線、以及晶片良率皆有負面的影響。因此，減少直通矽晶穿孔數目，在現今三維晶片設計中，是一個很重要的課題。本篇論文中，我們提出在每個控制步驟，我們總是能找到閒置的功能單元以及閒置的直通矽晶穿孔。我們可利用這些閒置的功能單元及閒置的直通矽晶穿孔構成替代路徑，取代原本直通矽晶穿孔之傳輸資料路徑，進而減少直通矽晶穿孔的數量。根據這個觀察，我們使用整數線性規劃的方式，去定義及解決此問題。給定高階合成的結果和時鐘週期的限制，我們進行後處理，充分利用替代路徑減少直通矽晶穿孔的數量。與既有文獻方法相比，我們能更進一步減少直通矽晶穿孔的數量，而且不影響其電路性能。

關鍵字

後處理；閒置功能單元；三維晶片，直通矽晶穿孔；高階合成

並列摘要

In the design of three-dimensional integrated circuits (3D ICs), through-silicon-vias (TSVs) are used for data transfer across layers. However, TSVs act as obstacles during the stage of placement and routing and have a negative impact on chip yield. Therefore, TSV count minimization is an important topic for 3D IC design. In this thesis, we demonstrate that, at each control step, there often exist idle functional units and idle TSVs. If these idle functional units and idle TSVs can form alternative paths to replace direct TSVs for data transfers, the TSV count can be reduced. Based on the above observation, we propose an ILP (integer linear programming) approach to formally define and solve our problem. Given a high-level synthesis result and a clock period constraint, we use post-processing to utilize alternative paths for the minimization of TSV count. Compared with the previous work, experimental results show that our approach can further reduce TSV count without affecting the circuit performance.

並列關鍵字

High-Level Synthesis ； Through-Silicon-Vias ； 3D IC ； Idle Functional Units ； Post-Processing

參考文獻

[2] T.-Y. Chiang, S. J. Souri, C. O. Chui, and K. C. Saraswat, “Thermal Analysis of Heterogeneous 3-D ICs with Various Integration Scenarios,” IEEE International Electron Devices Meeting, pp. 681—684, 2001.

[3] D.H. Kim, S. Mukhopadhyay, and S. K. Lim, “Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs,” Proc. of ACM/IEEE International Workshop on System Level Interconnect Prediction, pp. 85—92, 2009.

[4] M. Mukherjee and R. Vemuri, “Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems,” Proc. of IEEE/ACM International Conference on Computer Design, pp. 222—227, 2004.

[6] T. Kim and X. Liu, “A Global Interconnect Reduction Technique during High Level Synthesis”, Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 695–700, 2010.

[7] G.D. Micheli, “Synthesis and Optimization of Digital Circuits”, Kluwer Academic Publishers, 1994.

國際替代計量

利用替代路徑最小化三維晶片直通矽晶穿孔數目之方法研究

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