用於三維積體電路之溫度導向平面規劃的散熱型矽晶穿孔面積融合方法

隨著科技日新月異，製程的進步使得元件尺寸逐漸縮小，積體電路（integrated circuit）來到了奈米（nanometer）製程技術的時代，惟元件尺寸的精進已接近其物理極限。除此之外，晶片內部連線所造成的延遲也日益嚴重，使得整個晶片的效能也出現了瓶頸。因此，現今的晶片設計上，設計者正朝著另一角度的思維開發新一代的設計技術。三維積體電路（three dimensional integrated circuit）被視為能有效地改善上述問題的一項技術。然而，晶片從二維架構轉變為三維架構，雖然能有較好的面積、效能和功率消耗，但也引發出許多問題，溫度就是其中一項重要且不可忽略的議題。溫度議題的起因主要來自於堆疊技術易造成晶片中某些位置不易散熱，而晶片內部嚴重過熱將導致晶片毀損。插入散熱型矽晶穿孔（thermal through-silicon-via）於三維積體電路內部是一項可以有效解決三維積體電路內部散熱問題的技術。由於散熱型矽晶穿孔的尺寸遠大於標準元件的尺寸，所以如果在實體設計初期即適當地規劃散熱型矽晶穿孔的位置，便可以提早避免因擺置散熱型矽晶穿孔空間不足而造成設計佈局需要大幅變動，因此有許多研究提出在平面規劃（floorplanning）階段以推開電路區塊（block）並插入散熱型矽晶穿孔方式解決散熱的問題。本論文中，提供一個不同於以往的設計思維。在平面擺置之前即估計需要插入的散熱型矽晶穿孔數量，並根據這些數量擴大電路區塊後再進行平面規劃。平面規劃過程中除了須考量傳統面積及線長的最佳化外，還須同時考量電路區塊擴大區域的融合（fusion）程度，以期使用最少的散熱型矽晶穿孔數量達到要求的晶片內部目標溫度。

關鍵字

溫度；三維積體電路；平面規劃

並列摘要

As the process technology advances, the device size of integrated circuits continues to shrink into the nanometer scale. However, the device size is nearing its physical limits. Besides, interconnect delays are also growing, incurring the bottleneck of chip performance. Therefore, designers are thinking of moving to another point to develop a new generation of design technologies. Three dimensional integrated circuits (3D IC) are proposed as one technology to solve these problems. However, although 3D IC designs have better chip size, performance, and power consumption than 2D IC designs have, many emergent issues are occurred. Temperature is one of important issues and cannot be ignored. The temperature issue is mainly from the stacking technology which makes the thermal inside a chip cannot be dissipated easily. Thus, an overheating chip will incur the chip failed. Thermal through-silicon-via (TTSV) insertion technology is an effective method to dissipate the thermal in 3D IC. Since the size of a TTSV is much larger than that of a standard cell, space shortage and layout modification can be avoided if the TTSV location are planned in an early physical design stage. Thus, many researches proposed TTSV insertion by a push-block method to solve this issue during floorplanning. In this thesis, we propose a new viewpoint for TTSV insertion. The required number of TTSVs for each block is estimated and is used to enlarge the block before floorplanning. During floorplanning, we not only minimize area and wirelength, but also maximize the effect of fusion of TTSV area. Our objective is to satisfy the target temperature inside a chip with minimum number of TTSVs.

並列關鍵字

floorplan ； thermal ； 3DIC

參考文獻

[1] Jian-Qiang Lu, “3-D Hyperintegration and Packing Technologies for Micro-Nano Systems,” Proc. IEEE, January, 2009, pp. 18 – 30.

[2] THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009.

[3] Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan, “TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization,” in Proc. Design Automation Conf., 2010, pp. 803 – 807.

[5] Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu, “ILP-based inter-die routing for 3D ICs,” in Proc. Asia South Pacific Des. Auto. Conf., 2011, pp.330 – 335.

[9] Zhang Xu and Jiang Xiaohong, “Redundant Vias Insertion for Performance Enhancement in 3D ICs,” IEICE Trans. on electronic, 2008, pp. 509 – 519.

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用於三維積體電路之溫度導向平面規劃的散熱型矽晶穿孔面積融合方法

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