Functional engineering change, or engineering change order (ECO), is a popular technique for rectifying design errors after late design stages. This dissertation proposes a complete functional ECO flow from gate-level functional rectification to physical-level patch circuit realization. First, we present a new approach to multi-error circuit rectification. In this dissertation, we propose a two-phase approach: 1) discovering the functional matches in two circuits followed by 2) determining the final patch circuits from the derived matches. Our approach discovers functional matches by coordinating SAT-sweeping, cut-matching and single-fix rectification algorithms. Then, we conduct two approaches, which are pattern-guided patch selection and redundant patch removal algorithms, to determine the final patch circuit. The experimental results on public benchmark and industrial circuits demonstrate that our approach outperforms state-of-the-art engineering change engines. After generating the patch circuits, an ECO re-mapping flow is proposed to realize the patches. ECO re-mapping is a key step to realize patch functions on a layout database. It implements a given patch function with limited spare cells. Our ECO re-mapping flow includes a resource-constraint-aware technology mapper and a fast incremental router for wire-length optimization. To effectively utilize the constrained resources, we adopt the pseudo-Boolean techniques to search for feasible solutions when the spare cells are sparse. The experimental results show that our ECO re-mapping engine can outperform the previous tool in both runtime and routing costs.