同時考量邏輯功能轉換和時序修正的工程變更指令技術

現今超大型積體電路的製程技術日新月異，相對的電路複雜度也提升的許多，若是晶片部分功能發生瑕疵而需重新設計，以往做法都得經過繁雜的設計流程才能完成晶片修正，為了避免繁雜的設計流程並且加快完成晶片修正，在工程變更指令 (Engineering Change Order)階段修正晶片錯誤是有效且快速的方式。工程變更指令階段，是在擺置階段(Placement&Route)完成後，利用預留元件(spare cell)重新繞線，也就是修改原始電路的連線關係(netlist)，來達成設計者想做的電路變更，而常見的電路變更分為兩種，邏輯功能轉換(Functional Change)以及時序最佳化(Timing Optimization)。本篇論文提出了一個同時完成邏輯功能轉換並且完成時序最佳化的方法，第一階段先完成邏輯功能轉換，針對給定預留元件(spare cell)之位置、類型與數量的情況下，對每個預留元件給予權重，在給予權重的同時將時序影響加入考量，利用匹配方法挑選適合的預留元件來完成邏輯功能轉換並且是以電路修改成本最小化為導向，第二階段分析在邏輯功能轉換後的電路是否有時序違規，針對違反時脈限制的路徑藉由插入緩衝器或者是改變這些路徑上的邏輯閘大小來達到符合時脈限制目的。我們的演算法在測試檔案中可以完成所指定的邏輯功能轉換，並且有效的解決大部分違反時脈限制的路徑，而且執行所需時間都是很短的，代表本篇論文提供的演算法是相當有效的。

關鍵字

預留元件；工程變更指令

並列摘要

In the VLSI design process, designers use spare cells when they have to make functional changes or fix timing problems. Engineering Change Order (ECO), is a technique after the placement stage, we can use the spare cells in the chip by changing the netlist information to solve functional change problem and timing optimization problem. In this paper, we present an efficient approach to consider functional change problem and timing optimization problem at same time, the proposed approach includes two stages (1) functional change and (2) timing optimization. In first stage we conduct spare cells analyze, give the cost on those spare cells that we may select, and we modify the matching algorithm to solve spare cell selection with the goal of minimize the increase in wirelength. The second stage we conduct timing analyze, find all of path that have timing violation and solve those paths by applying gate sizing and buffer insertion techniques. Experimental results are based on five industry benchmarks. The results show that our approach is effective and efficient in fixing the functional change problem and timing optimization problem.

並列關鍵字

engineering change order ； spare cell

參考文獻

[2] G. D. Micheli: Synthesis and optimization of digital circuits, McGraw-Hill, 1994.

[4] K. Keutzer, “DAGON: Technology binding and local optimization by DAG matching,” in Proceedings of Design Automation Conference, pp. 341-347, 1987.

[8] N.A. Modi, M. Marek-Sadowska, “ECO-Map: Technology remapping for post-mask ECO using simulated annealing,” in Proceedings of International Conference on Computer Design, pp. 652-657, 2008.

[10] A. Kumar, K. Chakrabarty, C.R. Mohan, “An ECO Technique for Removing Crosstalk Violations in Clock Networks,” in Proceedings of VLSI Design, pp. 283-288, 2007.

[11] I.H.-R Jiang, H.-Y Chang, L.G Chang, H.-B. Hung, “Matching-based minimum-cost spare cell selection for design changes,” in Proceedings of Design Automation Conference, pp.26-31, 2009.

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同時考量邏輯功能轉換和時序修正的工程變更指令技術

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