針對時脈閘控與工程變更設計之有效率的關鍵時序分析與函數彈性勘查

Efficient Timing Criticality Analysis and Functional Flexibility Exploration for Clock Gating and ECO Designs

郭育旻(Yu-Min Kuo)

指導教授 ： 張世杰

國立清華大學/電機資訊學院/資訊工程學系/博士(2009年)

摘要

在這篇論文中，我們研究要達到成功電路時序優化所需要的二個重要主題。第一個主題是快速且準確的時序分析，而第二個主題是函數彈性的探索以便達到設計的時序優化和功能更正。首先，在先進的超大型積體電路設計流程中，準確的時序分析為電路優化之主要關鍵，要改進時序分析引擎的運行時間，我們首先提出時間布林特徵函數，它是一個非常高效率的表示方法尤其是應用在時間自動測試向量產生和電路延遲計算。基於這個有效率的分析工具，然後我們提出一個針對電源閘控設計的時序分析方法，並考慮去耦電容的插入及隨著時間變化的電壓下降問題。另外，為了改進電路的時序，我們從電路中訊號的相關性來得到函數彈性。使用時脈閘控的彈性，我們針對循序電路提出反覆優化技術使時序改善。使用將電路邏輯的輸入端連接到電源端或接地端的彈性，我們針對工程變更問題提出一個反覆方法得到可實作的電路分解。

關鍵字

時序分析 ； 電源閘控 ； 時脈閘控 ； 工程變更

並列摘要

In this thesis, we explore two essential topics required for a successful circuit timing optimization. The first topic is a fast but accurate timing analysis while the second topic is the functional flexibility so as to achieve timing optimization and functional correction of a design. First of all, the accurate timing is extremely crucial in the advanced VLSI design process for the circuit optimization. To improve the run time of a timing analysis engine, we first present a very efficient formula of timed Boolean characteristic functions for timed automatic test pattern generation and circuit delay computation. With this very efficient analysis tool, we then present a timing analysis approach for power gating designs considering the decoupling capacitance insertion and the time-varying IR drop issue. In addition, to improve the timing of a circuit, we propose to optimize the circuit by utilizing the flexibility from functional correlations. Using the flexibility of the clock gating, we propose an iterative optimization technique to minimize the overall timing for a sequential circuit. Using the flexibility of tying inputs to Vdd or Gnd, we propose an iterative method to generate feasible mapping solutions for the EC problem.

並列關鍵字

Timing analysis ； Power gating ； Clock gating ； Engineering change

參考文獻

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