針對確定性多核心指令集模擬之關鍵區間層級的時間同步方法

A Critical-Section-Level Timing Synchronization Approach for Deterministic Multi-Core Instruction-Set Simulations

游凡緯(Fan-Wei Yu)

指導教授 ： 蔡仁松 ； 李哲榮

國立清華大學/電機資訊學院/資訊工程學系/碩士(2012年)

https://doi.org/10.6843/NTHU.2012.00037

摘要

本篇論文提出了一個針對確定性多核心指令集模擬之關鍵區域層級的時間同步方法，透過同步在每一個鎖的存取，而不是在每一個共享變數的存取，並用一個簡單的鎖使用狀態管理機制，我們的方法可以顯著提高模擬效能，同時使所有關鍵區間執行在一個確定的順序。實驗顯示，我們的方法比起共享變數的同步方法平均快了295％，而我們的方法可以有效地促進系統層級的軟體/硬體協同模擬。

關鍵字

確定性 ； 多核心指令集模擬 ； 時間同步

並列摘要

This thesis proposes a Critical-Section-Level timing synchronization approach for deterministic Multi-Core Instruction-Set Simulation (MCISS). By synchronizing at each lock access instead of every shared-variable access and with a simple lock usage status managing scheme, our approach significantly improves simulation performance while having all critical sections executed in a deterministic order. Experiments show that our approach performs in average 295% faster than the shared-variable synchronization approach and the approach can effectively facilitate system-level software/hardware co-simulation.

並列關鍵字

Deterministic ； Multi-core instruction-set simulation ； Timing Synchronization

參考文獻

[4] M.-H. Wu, C.-Y. Fu, P.-C. Wang, and R.-S. Tsay, “An effective synchronization approach for fast and accurate multi-core instruction-set simulation,” in EMSOFT ’09: Proceedings of the seventh ACM international conference on Embedded software, 2009, p. 197.

[5] M.-H. Wu, P.-C. Wang, C.-Y. Fu, and R.-S. Tsay, “A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation,” in 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 2011, pp. 339–344.

[10] M. Reshadi, P. Mishra, and N. Dutt, “Instruction set compiled simulation: a technique for fast and flexible instruction set simulation,” in Design Automation Conference, 2003. Proceedings, 2003, pp. 758– 763.

[11] J. Schnerr, O. Bringmann, and W. Rosenstiel, “Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs,” in Proceedings of the conference on Design, Automation and Test in Europe - Volume 2, 2005, pp. 792–797.

[16] M. T. Yourst, “PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator,” in Performance Analysis of Systems & Software, 2007. ISPASS 2007. IEEE International Symposium on, 2007, pp. 23–34.