具功率感知的視訊編解碼器系統之設計與實現

Design and Implementation of Power-Aware Video Codec Systems

曾博志(Po-Chih Tseng)

指導教授 ： 陳良基

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2005年)

https://doi.org/10.6342/NTU.2005.01804

摘要

在本論文，視訊編解碼器系統中的兩個主要功率消耗來源，編解碼器核心與框架緩衝器存取，被三個研究主題所涵蓋。在編解碼器核心方面，具功率感知的有彈性視訊編解碼器系統與具功率感知的MPEG-4視訊編碼器系統的設計與實現分別在第一部分與第二部分中進行研究。而在框架緩衝器存取方面，針對框架緩衝器存取的嵌入式壓縮則在第三部分中做考慮。
具功率感知的視訊編解碼器系統之重要性在第一章中做介紹，而在本論文所採用的低功率設計技巧則在第二章中做說明。第三章(第一部分)討論針對具功率感知的有彈性視訊編解碼器系統的設計方法，而第四章(第一部分)則以離散小波轉換為標的來發展針對具功率感知的有彈性視訊編解碼器系統的特殊功能可重組化硬體加速器。接著，針對具功率感知的MPEG-4視訊編碼器系統的設計方法在第五章(第二部分)中做探討，而幾個具主宰性大量運算的任務之設計則在接下來的三章中做說明，包含了第六章(第二部分)的低功率全域搜尋移動估計處理器，第七章(第二部分)的多重模式內容相關低功率移動估計處理器，以及第八章(第二部分)的內容相關低功率離散餘弦轉換暨量化處理器。然後，第九章(第三部分)考慮針對框架緩衝器存取的低複雜度多重模式嵌入式壓縮引擎。本論文的主要貢獻與未來方向於第十章中做結論。最後，一個針對影像與視訊編碼的硬體架構演進之概括論述則在第十一章中做附錄參考。

關鍵字

設計 ； 視訊編解碼器 ； 實現 ； 功率 ； 視訊編解碼器系統 ； 具功率感知

並列摘要

In this dissertation, two major sources of power dissipation in video codec systems, the codec core and the frame buffer access, are covered by three research topics. For codec core, the design and implementation of power-aware flexible video codec system and power-aware MPEG-4 video encoder system are investigated in Part I and Part II respectively. As for frame buffer access, the embedded compression for frame buffer access is considered in Part III.
The importance of power-aware video codec systems are introduced in Chapter 1. The low-power design techniques to be applied in this dissertation are then reviewed in Chapter 2. Chapter 3 (of Part I) discusses the design approach for power-aware flexible video codec system, and Chapter 4 (of Part I) targets the DWT for the development of function-specific reconfigurable hardware accelerator for power-aware flexible video codec system. The design approach for power-aware MPEG-4 video encoder system is investigated in Chapter 5 (of Part II), and the designs of dominating computation-intensive tasks are described in following three chapters, including the low-power full search ME processor in Chapter 6 (of Part II), the multi-mode content-dependent low-power ME processor in Chapter 7 (of Part II), and the content-dependent low-power DCTQ processor in Chapter 8 (of Part II). Then, in Chapter 9 (of Part III), the low-complexity multi-mode embedded compression engine is considered for frame buffer access. The principal contributions and future directions are concluded in Chapter 10. Finally, an appendix about the survey of advances in hardware architectures for image and video coding is given in Chapter 11.

並列關鍵字

Video Codec System ； Power-Aware ； Design ； Implementation ； Video Codec ； Power

參考文獻

[3] JPEG 2000 Image Coding System, ISO/IEC FDIS15444-1, 2000.

[8] Video Coding for Low Bit Rate Communication, ITU-T Recommendation H.263, 1998.

[11] International Technology Roadmap for Semiconductors 2003 Edition,In-ternational Technology Roadmap for Semiconductors (ITRS), 2003.

Papers of IEEE International Solid-State Circuits Conference, 1998, pp. 36–37.

[14] T. Xanthopoulos and A. P. Chandrakasan, “A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization,” IEEE Journal of Solid-State Circuits, vol. 35, no. 5, pp. 740–750, May 2000.