適用於315/433/868/915 MHz ISM頻帶之分數型頻率合成器

A Fractional-N Frequency Synthesizer for 315/433/868/915 MHz ISM Bands

李昉亭(Fang-Ting Lee)

指導教授 ： 呂學士

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.10425

摘要

近年來，以鎖相迴路為主的頻率合成器大量被使用在無線通訊系統中。由於整數型鎖相迴路本身有鎖定時間與頻率解析度的設計衝突，因此分數型頻率合成器較常被使用在無線應用中，因為它可以消除迴路頻寬與頻率解析度的設計衝突。

本論文的主題是利用標準的0.35微米CMOS製程來設計及實現三個分數型頻率合成器。電路實作的內容概要如下：

第一塊電路是一個運作於915 MHz的分數型頻率合成器。該頻率合成器適用於低功率及高整合度的應用。電路中所採用的容值倍增器可將小容值乘以某個倍數放大，如此一來即可用較小的容值來產生等效的大容值，有效減少迴路濾波器的晶片面積以利單晶片整合。為了降低功率消耗，該電路採用環狀震盪器作為壓控震盪器。

在第二塊電路實作中，我們實現一個可運作於315/433/868/915 MHz ISM頻帶的分數型頻率合成器。該電路中使用LC震盪器及三階的三角積分調變器來改善相位雜訊。量測結果顯示四個ISM操作頻段皆有涵蓋到，並有較低的相位雜訊。

在第三塊架構中，我們實現一個利用第四章分數型頻率合成器實現的高斯頻移鍵控調變器。直接對三角積分調變器的輸入端進行調變是個可輕易達成數位調變，並同時維持較低的相位雜訊的架構。另外，我們也使用雙點調變的機制，在壓控震盪器的輸入端增設一條具高通特性的調變路徑，以提升資料傳輸率，使其不被鎖相迴路的頻寬限制住。

關鍵字

鎖相迴路 ； 頻率合成器 ； 射頻 ； 積體電路 ； 三角積分調變器

並列摘要

In recent years, PLL-based frequency synthesizers have been widely used in wireless communication systems. However, the integer-N PLLs suffer from several tradeoffs, such as the tradeoff between the tuning speed and the frequency resolution. In order to break the tie between the reference frequency and the step size, fractional-N synthesizers are mostly adopted in many communication applications.

This thesis presents the design and implementation of CMOS integrated fractional-N frequency synthesizers. Three fractional-N frequency synthesizers have been implemented and fabricated in standard 0.35-um CMOS process.

The first chip is a 915-MHz fractional-N frequency synthesizer targeting the low power and high integration applications. This prototype achieves full integration by using capacitance multiplier to scale up a small capacitance by a desired factor. This technique effectively reduces the integrating capacitor in the loop filter, which is often an integration bottleneck of the PLL. A ring oscillator is also employed in order to save power consumption.

The second chip is a fractional-N frequency synthesizer for 315/433/868/915 MHz ISM applications. The use of an LC VCO and a third-order delta-sigma modulator ensures the spectral purity. The measurement results indicate the entire coverage of the expected frequency bands, and the measured phase noise performs well.

The third chip is a GFSK modulator using the fractional-N frequency synthesizer introduced in chapter 4. Directly modulating the input of the delta-sigma modulator allows digital frequency modulation to be easily accomplished while simultaneously achieve good noise performance. Moreover, the two-point modulation technique creates a second modulation path to inject the transmission signals into the second tuning port of the VCO. Using such technique, the maximum available data rate can exceed the PLL loop bandwidth.

並列關鍵字

PLL ； phase-locked loop ； frequency synthesizer ； delta-sigma ； GFSK ； transmitter ； ISM ； RF ； radio-frequency

參考文獻

[2.4] F. Gardner, “Charge-pump phase-lock loops,” IEEE Trans. Communication, vol. 28, pp. 1849-1858, Nov. 1980

[2.6] T. S. Aytur and B. Razavi, “A 2-GHz, 6-mW BiCMOS Frequency Synthesizer,” IEEE J. Solid-State Circuits, vol. 30, pp.1457-1462, Dec. 1995

[2.7] C. Vaucher and D. Kasperkovitz, “A wide-band tuning system for fully integrated satellite receivers,” IEEE J. Solid-State Circuits, pp.987-997, July 1998.

[2.8] J. Craninckx and M.S.J. Steyaert, “A 1.75GHz/3V dual-modulus divide -by-128/129 prescaler in 0.7-μm CMOS,” IEEE J. Solid-State Circuits, pp.890-897, July 1996.

[2.9] B. Razavi, Design of Analog CMOS Integrated Circuits, New-York: McGraw-Hill, 2001.